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TPS70248PWPR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS70248PWPR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20
TPS70248PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 2 | VIN1 | power_in | Input voltage of regulator 1, shared with pin 3; absolute maximum input range is -0.3 V to +7 V and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V. |
| 3 | VIN1 | power_in | Input voltage of regulator 1, shared with pin 2; absolute maximum input range is -0.3 V to +7 V. |
| 4 | MR | input | Active-low manual reset input that is pulled up internally with a 6 µA current to VIN1; pulling it low triggers a POR (RESET) event. |
| 5 | EN1 | input | Active-low enable for regulator 1 (VOUT1); a high level shuts regulator 1 down and a low level enables it, with absolute maximum voltage of -0.3 V to +7 V. |
| 6 | EN2 | input | Active-low enable for regulator 2 (VOUT2); a high level shuts regulator 2 down and a low level enables it, with absolute maximum voltage of -0.3 V to +7 V. |
| 7 | RESET | output | Active-low, open-drain SVS power-on-reset output that requires an external pull-up resistor and may be left floating if unused; maximum voltage is 7 V. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | VIN2 | power_in | Input voltage of regulator 2, shared with pin 10; absolute maximum input range is -0.3 V to +7 V. |
| 10 | VIN2 | power_in | Input voltage of regulator 2, shared with pin 9; absolute maximum input range is -0.3 V to +7 V. |
| 11 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 12 | VOUT2 | power_out | Output of regulator 2, shared with pin 13; regulator 2 supplies up to 250 mA and VOUT2 absolute maximum is 5.5 V. |
| 13 | VOUT2 | power_out | Output of regulator 2, shared with pin 12; regulator 2 supplies up to 250 mA and VOUT2 absolute maximum is 5.5 V. |
| 14 | VSENSE2/FB2 | input | Regulator 2 output sense for fixed-voltage versions, which must be connected as close as possible to VOUT2, and feedback input for the adjustable version, which connects to the external resistor divider; absolute maximum is 5.5 V. |
| 15 | PG2 | output | Open-drain power-good output for regulator 2 that goes low when VOUT2 is below 95% of its nominal regulated voltage and requires a pull-up resistor; maximum voltage is 7 V. |
| 16 | PG1 | output | Open-drain power-good output for regulator 1 that goes low when VOUT1 is below 95% of its nominal regulated voltage and requires a pull-up resistor; maximum voltage is 7 V. |
| 17 | VSENSE1/FB1 | input | Regulator 1 output sense for fixed-voltage versions, which must be connected as close as possible to VOUT1, and feedback input for the adjustable version, which connects to the external resistor divider; absolute maximum is 5.5 V. |
| 18 | VOUT1 | power_out | Output of regulator 1, shared with pin 19; regulator 1 supplies up to 500 mA and VOUT1 absolute maximum is 5.5 V. |
| 19 | VOUT1 | power_out | Output of regulator 1, shared with pin 18; regulator 1 supplies up to 500 mA and VOUT1 absolute maximum is 5.5 V. |
| 20 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS70248PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps70248pwpr-etched.step/tps70248pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps70248pwpr.step/tps70248pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
e5efd81384505990, retrieved 2026-10-12, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS70248PWPR
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20
TPS70248PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 2 | VIN1 | power_in | Input voltage of regulator 1, shared with pin 3; absolute maximum input range is -0.3 V to +7 V and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V. |
| 3 | VIN1 | power_in | Input voltage of regulator 1, shared with pin 2; absolute maximum input range is -0.3 V to +7 V. |
| 4 | MR | input | Active-low manual reset input that is pulled up internally with a 6 µA current to VIN1; pulling it low triggers a POR (RESET) event. |
| 5 | EN1 | input | Active-low enable for regulator 1 (VOUT1); a high level shuts regulator 1 down and a low level enables it, with absolute maximum voltage of -0.3 V to +7 V. |
| 6 | EN2 | input | Active-low enable for regulator 2 (VOUT2); a high level shuts regulator 2 down and a low level enables it, with absolute maximum voltage of -0.3 V to +7 V. |
| 7 | RESET | output | Active-low, open-drain SVS power-on-reset output that requires an external pull-up resistor and may be left floating if unused; maximum voltage is 7 V. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | VIN2 | power_in | Input voltage of regulator 2, shared with pin 10; absolute maximum input range is -0.3 V to +7 V. |
| 10 | VIN2 | power_in | Input voltage of regulator 2, shared with pin 9; absolute maximum input range is -0.3 V to +7 V. |
| 11 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 12 | VOUT2 | power_out | Output of regulator 2, shared with pin 13; regulator 2 supplies up to 250 mA and VOUT2 absolute maximum is 5.5 V. |
| 13 | VOUT2 | power_out | Output of regulator 2, shared with pin 12; regulator 2 supplies up to 250 mA and VOUT2 absolute maximum is 5.5 V. |
| 14 | VSENSE2/FB2 | input | Regulator 2 output sense for fixed-voltage versions, which must be connected as close as possible to VOUT2, and feedback input for the adjustable version, which connects to the external resistor divider; absolute maximum is 5.5 V. |
| 15 | PG2 | output | Open-drain power-good output for regulator 2 that goes low when VOUT2 is below 95% of its nominal regulated voltage and requires a pull-up resistor; maximum voltage is 7 V. |
| 16 | PG1 | output | Open-drain power-good output for regulator 1 that goes low when VOUT1 is below 95% of its nominal regulated voltage and requires a pull-up resistor; maximum voltage is 7 V. |
| 17 | VSENSE1/FB1 | input | Regulator 1 output sense for fixed-voltage versions, which must be connected as close as possible to VOUT1, and feedback input for the adjustable version, which connects to the external resistor divider; absolute maximum is 5.5 V. |
| 18 | VOUT1 | power_out | Output of regulator 1, shared with pin 19; regulator 1 supplies up to 500 mA and VOUT1 absolute maximum is 5.5 V. |
| 19 | VOUT1 | power_out | Output of regulator 1, shared with pin 18; regulator 1 supplies up to 500 mA and VOUT1 absolute maximum is 5.5 V. |
| 20 | NC | unconnected | No internal connection; the pin may be left unconnected. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
## CAD (KiCad official)
- Symbol: `TPS70248PWPR`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps70248pwpr-etched.step` / `tps70248pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps70248pwpr.step` / `tps70248pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps70248pwpr.pdf) (38 pp, sha256 `e5efd81384505990`, retrieved 2026-10-12, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps70248pwpr-datasheet.pdf)