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TPS70245PWP

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS70245PWP

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20

TPS70245PWP from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection on this pin.
2 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1, with absolute maximum input range of -0.3 V to +7 V.
3 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1, with absolute maximum input range of -0.3 V to +7 V.
4 MR input Manual reset input, active low, pulled up internally to VIN1 with a 6 µA pull-up current.
5 EN1 input Active low enable for VOUT1; a high level shuts down regulator 1, and absolute maximum voltage on EN1 is -0.3 V to +7 V.
6 EN2 input Active low enable for VOUT2; a high level shuts down regulator 2, and absolute maximum voltage on EN2 is -0.3 V to +7 V.
7 RESET output Open drain active low power-on reset (SVS) output that requires an external pull-up resistor and may be left floating if unused; maximum RESET voltage is 7 V.
8 GND power_in Ground reference for the device.
9 VIN2 power_in Input voltage of regulator 2.
10 VIN2 power_in Input voltage of regulator 2.
11 NC unconnected No internal connection on this pin.
12 VOUT2 power_out Output voltage of regulator 2, rated for up to 250 mA, with absolute maximum output voltage of 5.5 V.
13 VOUT2 power_out Output voltage of regulator 2, rated for up to 250 mA, with absolute maximum output voltage of 5.5 V.
14 VSENSE2/FB2 input Regulator 2 output voltage sense for fixed-voltage versions, or feedback input for the adjustable version, which must be kept as short as possible and away from noise pickup.
15 PG2 output Open drain power-good output for regulator 2 that goes low when VOUT2 is below 95% of its nominal regulated voltage and requires a pull-up resistor.
16 PG1 output Open drain power-good output for regulator 1 that goes low when VOUT1 is below 95% of its nominal regulated voltage and requires a pull-up resistor.
17 VSENSE1/FB1 input Regulator 1 output voltage sense for fixed-voltage versions, or feedback input for the adjustable version, which must be kept as short as possible and away from noise pickup.
18 VOUT1 power_out Output voltage of regulator 1, rated for up to 500 mA, with absolute maximum output voltage of 5.5 V.
19 VOUT1 power_out Output voltage of regulator 1, rated for up to 500 mA, with absolute maximum output voltage of 5.5 V.
20 NC unconnected No internal connection on this pin.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage, 1.2 V output (regulator 2, VOUT2) VO 1.176 1.224 V 2.7V < VIN < 6V, over junction temperature range 5
Output voltage, 3.3 V output (regulator 1, VOUT1) VO 3.234 3.366 V 4.3V < VIN < 6V, over junction temperature range 5
Reference voltage, FB connected to VO 1.196 1.22 1.244 V 2.7V < VIN < 6V, FB connected to VO; typ at TJ = +25°C, min/max over temperature 5
Output voltage line regulation (regulator 1 and regulator 2) ΔVO/VO 0.1 %/V VO + 1V < VIN ≤ 6V 5
Quiescent current (GND current), regulator 1 and regulator 2 230 μA EN1 = EN2 = 0V 5
Output current limit, regulator 1 1.6 1.9 A VOUT = 0V 5
Output current limit, regulator 2 0.75 1 A VOUT = 0V 5
Undervoltage lockout (UVLO) threshold 2.4 2.65 V 5
RESET minimum input voltage for valid RESET 1 1.3 V IRESET = 300μA, V(RESET) ≤ 0.8V 5
RESET pulse duration, t(RESET) t(RESET) 80 120 160 ms 5
RESET output low voltage 0.15 0.4 V VIN = 3.5V, I(RESET) = 1mA 5
RESET leakage current 1 μA V(RESET) = 6V 5
Minimum input voltage for valid PGx 1 1.3 V I(PGx) = 300μA, V(PGx) ≤ 0.8V 6
PGx trip threshold voltage 92 95 98 %VOUT VO decreasing 6
PGx output low voltage 0.15 0.4 V VIN = 2.7V, I(PGx) = 1mA 6
PGx leakage current 1 μA V(PGx) = 6V 6
High-level ENx input voltage 2 V 6
Low-level ENx input voltage 0.7 V 6
Input current (ENx) -1 1 μA 6
High-level MR input voltage 2 V 6
Low-level MR input voltage 0.7 V 6
Dropout voltage, VOUT1 170 275 mV IO = 500mA, VIN1 = 3.2V; typ at TJ = +25°C, max over temperature range 6
Quiescent current (GND current), regulator 1 and regulator 2, typical 190 μA EN1 = EN2 = 0V, TJ = +25°C 5
Load regulation for VOUT1 and VOUT2 1 mV TJ = +25°C 5
Output voltage line regulation, typical ΔVO/VO 0.01 %/V VO + 1V < VIN ≤ 6V, TJ = +25°C 5
Output noise voltage, regulator 1 Vn 65 μVRMS BW = 300Hz to 50kHz, CO = 33μF, TJ = +25°C 5
Output noise voltage, regulator 2 Vn 65 μVRMS BW = 300Hz to 50kHz, CO = 33μF, TJ = +25°C 5
Power-supply ripple rejection, regulator 1 PSRR 60 dB f = 1kHz, CO = 33μF, IOUT1 = 500mA, TJ = +25°C 5
Power-supply ripple rejection, regulator 2 PSRR 50 dB f = 1kHz, CO = 33μF, IOUT2 = 250mA, TJ = +25°C 5
Thermal shutdown junction temperature 150 °C 5
Input voltage, VI (regulator 1 and 2) VI 2.7 6 V 4
Output current, IO (regulator 1) IO 0 500 mA 4
Output current, IO (regulator 2) IO 0 250 mA 4
Operating virtual junction temperature TJ -40 125 °C 4
Input voltage range, VIN1 and VIN2 VIN1, VIN2 -0.3 7 V 3
Voltage range at EN1, EN2 EN1, EN2 -0.3 7 V 3
Output voltage range (VOUT1, VSENSE1) VOUT1, VSENSE1 5.5 V 3
Output voltage range (VOUT2, VSENSE2) VOUT2, VSENSE2 5.5 V 3
Maximum RESET, PG1, PG2 voltage 7 V 3
Operating virtual junction temperature range TJ -40 150 °C 3
Storage temperature range Tstg -65 150 °C 3
Junction-to-ambient thermal resistance (RθJA) RθJA 32.6 °C/W 20-terminal PWP, no airflow 28
Continuous total power dissipation 3.067 W PWP, 0 CFM airflow, TA ≤ +25°C; derating 30.67 mW/°C 4

CAD (KiCad official)

  • Symbol: TPS70245PWP
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps70245pwp-etched.step / tps70245pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70245pwp.step / tps70245pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 442e41a4a4622bc2, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF