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TPS70202PWPR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS70202PWPR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20

TPS70202PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection; the datasheet states NC means no internal connection.
2 VIN1 power_in Input voltage of regulator 1; absolute maximum input range is -0.3 V to +7 V, and the UVLO keeps the regulators off until VIN1 reaches 2.5 V.
3 VIN1 power_in Input voltage of regulator 1; absolute maximum input range is -0.3 V to +7 V, and the UVLO keeps the regulators off until VIN1 reaches 2.5 V.
4 MR input Active-low manual reset input, pulled up internally with a 6μA pull-up current to VIN1; pulling it low triggers a POR (RESET).
5 EN1 input Active-low enable for VOUT1; a high level shuts down regulator 1 and a low level enables it.
6 EN2 input Active-low enable for VOUT2; a high level shuts down regulator 2 and a low level enables it.
7 RESET output Active-low, open-drain SVS power-on reset output that requires an external pull-up resistor and goes high impedance after a 120ms delay when MR is high.
8 GND power_in Ground pin; all voltages are referenced to network ground.
9 VIN2 power_in Input voltage of regulator 2; absolute maximum input range is -0.3 V to +7 V.
10 VIN2 power_in Input voltage of regulator 2; absolute maximum input range is -0.3 V to +7 V.
11 NC unconnected No connection; the datasheet states NC means no internal connection.
12 VOUT2 power_out Output voltage of regulator 2, which supplies up to 250mA.
13 VOUT2 power_out Output voltage of regulator 2, which supplies up to 250mA.
14 VSENSE2/FB2 input Regulator 2 feedback input for the adjustable TPS70202; must be connected to the external feedback resistor divider with a short, noise-shielded route.
15 PG2 output Open-drain power-good output for regulator 2 that goes low when VOUT2 is below 95% of its nominal voltage and requires a pull-up resistor.
16 PG1 output Open-drain power-good output for regulator 1 that goes low when VOUT1 is below 95% of its nominal voltage and requires a pull-up resistor.
17 VSENSE1/FB1 input Regulator 1 feedback input for the adjustable TPS70202; must be connected to the external feedback resistor divider with a short, noise-shielded route.
18 VOUT1 power_out Output voltage of regulator 1, which supplies up to 500mA.
19 VOUT1 power_out Output voltage of regulator 1, which supplies up to 500mA.
20 NC unconnected No connection; the datasheet states NC means no internal connection.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage, VI (regulator 1 and 2) VI 2.7 6 V 4
Output current, IO (regulator 1) IO 0 500 mA 4
Output current, IO (regulator 2) IO 0 250 mA 4
Output voltage range (for adjustable option) VO 1.22 5.5 V 4
Operating virtual junction temperature TJ -40 125 °C 4
Input voltage range VIN1, VIN2 -0.3 7 V 3
Voltage range at EN1, EN2 EN1, EN2 -0.3 7 V 3
Output voltage range (VOUT1, VSENSE1) VOUT1, VSENSE1 5.5 V 3
Output voltage range (VOUT2, VSENSE2) VOUT2, VSENSE2 5.5 V 3
Maximum RESET, PG1, PG2 voltage RESET, PG1, PG2 7 V 3
Operating virtual junction temperature range TJ -40 150 °C 3
Storage temperature range Tstg -65 150 °C 3
ESD rating, HBM 2 kV HBM 3
Reference voltage (FB connected to VO) VREF 1.196 1.244 V 2.7V < VIN < 6V, FB connected to VO 5
Quiescent current (GND current) for regulator 1 and regulator 2 IQ 230 μA EN1 = EN2 = 0V; see note (2): IO = 1mA to 500mA (reg 1), 1mA to 250mA (reg 2) 5
Output voltage line regulation (ΔVO/VO) 0.1 %/V VO + 1V < VIN ≤ 6V 5
Output current limit 1.6 1.9 A Regulator 1, VOUT = 0V 5
Output current limit 0.75 1 A Regulator 2, VOUT = 0V 5
UVLO threshold 2.4 2.65 V 5
Minimum input voltage for valid RESET 1 1.3 V IRESET = 300μA, V(RESET) ≤ 0.8V 5
RESET pulse duration t(RESET) 80 120 160 ms 5
RESET output low voltage 0.15 0.4 V VIN = 3.5V, I(RESET) = 1mA 5
Minimum input voltage for valid PGx 1 1.3 V I(PGx) = 300μA, V(PGx) ≤ 0.8V 6
Trip threshold voltage 92 95 98 %VOUT VO decreasing 6
PGx output low voltage 0.15 0.4 V VIN = 2.7V, I(PGx) = 1mA 6
High-level ENx input voltage 2 V 6
Low-level ENx input voltage 0.7 V 6
Input current (ENx) -1 1 μA 6
MR high-level input voltage 2 V 6
MR low-level input voltage 0.7 V 6
Dropout voltage (VOUT1 terminal) 275 mV IO = 500mA, VIN1 = 3.2V 6
Reference voltage (FB connected to VO) VREF 1.22 V 2.7V < VIN < 6V, FB connected to VO, TJ = +25°C 5
Quiescent current (GND current) for regulator 1 and regulator 2 IQ 190 μA TJ = +25°C, EN1 = EN2 = 0V 5
Output voltage line regulation (ΔVO/VO) 0.01 %/V VO + 1V < VIN ≤ 6V, TJ = +25°C 5
Load regulation for VOUT1 and VOUT2 1 mV TJ = +25°C 5
Output noise voltage (Vn), regulator 1 Vn 65 μVRMS BW = 300Hz to 50kHz, CO = 33μF, TJ = +25°C 5
Output noise voltage (Vn), regulator 2 Vn 65 μVRMS BW = 300Hz to 50kHz, CO = 33μF, TJ = +25°C 5
Thermal shutdown junction temperature 150 °C 5
Standby current, regulator 1 I(standby) 2 μA EN1 = VIN, EN2 = VI, TJ = +25°C 5
Standby current, regulator 2 I(standby) 6 μA EN1 = VIN, EN2 = VI 5
Power-supply ripple rejection, regulator 1 PSRR 60 dB f = 1kHz, CO = 33μF, IOUT1 = 500mA, TJ = +25°C 5
Power-supply ripple rejection, regulator 2 PSRR 50 dB f = 1kHz, CO = 33μF, IOUT2 = 250mA, TJ = +25°C 5
RESET input leakage current 1 μA V(RESET) = 6V 5
PG hysteresis voltage 0.5 %VOUT Measured at VO 6
PGx rising edge deglitch tr(PGx) 30 μs 6
PGx leakage current 1 μA V(PGx) = 6V 6
MR pull-up current source 6 μA 6
Dropout voltage (VOUT1 terminal) 170 mV IO = 500mA, VIN1 = 3.2V, TJ = +25°C 6
Peak output current (VOUT1) 750 mA 2ms pulse width 6
Discharge transistor current (VOUT1) 7.5 mA VOUT1 = 1.5V 6
Peak output current (VOUT2) 375 mA 2ms pulse width 6
Discharge transistor current (VOUT2) 7.5 mA VOUT2 = 1.5V 6
FB input current (TPS70202) 1 μA FB = 1.8V 6
Thermal resistance, junction-to-ambient (RθJA) RθJA 32.6 °C/W 20-terminal PWP, no airflow 28

CAD (KiCad official)

  • Symbol: TPS70202PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps70202pwpr-etched.step / tps70202pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70202pwpr.step / tps70202pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 442e41a4a4622bc2, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF