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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	22d ago
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package.json	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
page.json	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
README.md	Publish 0.1.0 · Ray	22d ago
tps70148pwpr-etched.glb	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
tps70148pwpr-etched.step	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
tps70148pwpr-hero.glb	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
tps70148pwpr-hero.overlay.json	tps70148pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
tps70148pwpr.glb	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	17d ago
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tps70148pwpr.step	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	17d ago

TPS70148PWPR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20

TPS70148PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No connection terminal (NC) per Table 1.
2	VIN1	power_in	Input voltage of regulator 1, with the internal bias also powered from VIN1; the regulators stay off until VIN1 reaches 2.5 V (UVLO), and absolute maximum input is -0.3 V to +7 V.
3	VIN1	power_in	Second input pin of regulator 1 (VIN1 is bonded to two pins); the regulators stay off until VIN1 reaches 2.5 V (UVLO), and absolute maximum input is -0.3 V to +7 V.
4	MR1	input	Manual reset input 1, active low, with an internal 6 mA pull-up current to VIN1; pulling it low triggers a POR (RESET).
5	MR2	input	Manual reset input 2, active low, with an internal 6 mA pull-up current to VIN1; pulling it low triggers a POR (RESET).
6	EN	input	Active-low enable: a high level puts the device in shutdown mode (input current reduced to about 1 mA at TJ = +25°C), and a low level enables it.
7	SEQ	input	Power-up sequence control: high or open makes VOUT2 power up first (VOUT1 enables near 83% of VOUT2), low makes VOUT1 power up first; the pin has an internal 6 mA pull-up to VIN1.
8	GND	power_in	Ground reference for the device.
9	VIN2	power_in	Input voltage of regulator 2, with absolute maximum input of -0.3 V to +7 V.
10	VIN2	power_in	Second input pin of regulator 2 (VIN2 is bonded to two pins), with absolute maximum input of -0.3 V to +7 V.
11	NC	unconnected	No connection terminal (NC) per Table 1.
12	VOUT2	power_out	Output voltage of regulator 2, which supplies up to 250 mA.
13	VOUT2	power_out	Output voltage of regulator 2 (second pin), which supplies up to 250 mA.
14	VSENSE2/FB2	input	Regulator 2 output sense for fixed-output versions, which must be connected to VOUT2 as short as possible, or feedback input for adjustable versions; RC filtering between this pin and VOUT2 is not recommended because it can cause oscillation.
15	RESET	output	Open-drain active-low SVS/power-on reset output that reflects VOUT2 and MR1/MR2 status, goes high impedance after a 120 ms delay once VOUT2 exceeds 95% of its regulated voltage with MR1 and MR2 high, and requires a pull-up resistor.
16	PG1	output	Open-drain active-high power-good output for regulator 1 that is low when VOUT1 is below 95% of its nominal regulated voltage and requires a pull-up resistor.
17	VSENSE1/FB1	input	Regulator 1 output sense for fixed-output versions, which must be connected to VOUT1 as short as possible, or feedback input for adjustable versions; RC filtering between this pin and VOUT1 is not recommended because it can cause oscillation.
18	VOUT1	power_out	Output voltage of regulator 1, which supplies up to 500 mA.
19	VOUT1	power_out	Output voltage of regulator 1 (second pin), which supplies up to 500 mA.
20	NC	unconnected	No connection terminal (NC) per Table 1.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20
Category	Power Management (PMIC)
Pins	21

CAD (KiCad official)

Symbol: TPS70148PWPR
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps70148pwpr-etched.step / tps70148pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70148pwpr.step / tps70148pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 d80cbe16566ccbe6, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF