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TPS65994ADRSLR

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Texas Instruments Power Management Specialized - PMIC, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS65994ADRSLR

Texas Instruments · Power Management Specialized - PMIC · VQFN-48-EP(6x6)

TPS65994ADRSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I2C3m_SCL output I2C master serial clock, open-drain output; tie to pullup voltage through a resistor whether used or unused.
2 GPIO4 bidirectional General purpose digital I/O that may be used as an ADC input; tie to PP5V or ground when unused.
3 VSYS power_in High-voltage sinking node in the system, used for reverse-current protection of the external sinking paths controlled by PA_GATE_VSYS and PB_GATE_VSYS.
4 PB_GATE_VSYS output Connects to the Port B N-ch MOSFET that has its source tied to VSYS.
5 PA_GATE_VSYS output Connects to the Port A N-ch MOSFET that has its source tied to VSYS.
6 PB_CC1 bidirectional I/O for USB Type-C and USB PD on Port B; filter noise with the recommended capacitor to GND.
7 PB_CC2 bidirectional I/O for USB Type-C and USB PD on Port B; filter noise with the recommended capacitor to GND.
8 GPIO9 output General purpose digital output (PROCHOT#); tie to PP5V or ground when unused.
9 GPIO2 bidirectional General purpose digital I/O; tie to PP5V or ground when unused.
10 GPIO8 bidirectional General purpose digital I/O; tie to PP5V or ground when unused.
11 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
12 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
13 PB_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port B; bypass with CVBUS to GND.
14 PB_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port B; bypass with CVBUS to GND.
15 PB_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port B; bypass with CVBUS to GND.
16 PB_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port B; bypass with CVBUS to GND.
17 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
18 PB_GATE_VBUS output Connects to the N-ch MOSFET that has its source tied to PB_VBUS.
19 PA_GATE_VBUS output Connects to the N-ch MOSFET that has its source tied to PA_VBUS.
20 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
21 PA_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port A; bypass with CVBUS to GND.
22 PA_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port A; bypass with CVBUS to GND.
23 PA_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port A; bypass with CVBUS to GND.
24 PA_VBUS bidirectional 5-V to 20-V input or 5-V output from PP5V on Port A; bypass with CVBUS to GND.
25 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
26 PP5V power_in 5-V system supply to VBUS and supply for the Px_CCy pins as VCONN.
27 GPIO7 bidirectional General purpose digital I/O; tie to PP5V or ground when unused.
28 GPIO3 bidirectional General purpose digital I/O; tie to PP5V or ground when unused.
29 GPIO6 bidirectional General purpose digital I/O; tie to PP5V or ground when unused.
30 PA_CC2 bidirectional I/O for USB Type-C and USB PD on Port A; filter noise with the recommended capacitor to GND.
31 PA_CC1 bidirectional I/O for USB Type-C and USB PD on Port A; filter noise with the recommended capacitor to GND.
32 VIN_3V3 power_in Supply for core circuitry and I/O; bypass with CVIN_3V3 to GND.
33 ADCIN1 input Configuration input; connect to a resistor divider to LDO_3V3.
34 LDO_3V3 power_out Output of supply switched from VIN_3V3 or the VBUS LDO; bypass with CLDO_3V3 to GND.
35 ADCIN2 input Configuration input; connect to a resistor divider to LDO_3V3.
36 GND power_in Ground; connect to the ground plane.
37 LDO_1V5 power_out Output of the CORE LDO, bypass with CLDO_1V5 to GND; this pin cannot source current to external circuits.
38 GPIO1 bidirectional General purpose digital I/O that may be used as DisplayPort HPD signal for Port A; tie to PP5V or ground when unused.
39 I2C2s_IRQ output I2C slave interrupt, active low; connect to external voltage through a pull-up resistor, can be reconfigured to GPIO11.
40 I2C_EC_SDA bidirectional I2C slave serial data, open-drain; tie to pullup voltage through a resistor, connect to the Embedded Controller, may be grounded if unused.
41 I2C2s_SCL input I2C slave serial clock input; tie to pull-up voltage through a resistor, may be grounded if unused.
42 I2C_EC_SCL input I2C slave serial clock input; tie to pullup voltage through a resistor, connect to the Embedded Controller, may be grounded if unused.
43 I2C_EC_IRQ output I2C slave interrupt, active low; connect to external voltage through a pull-up resistor and to the EC, can be reconfigured to GPIO10, may be grounded if unused.
44 I2C2s_SDA bidirectional I2C slave serial data, open-drain; tie to pullup voltage through a resistor, may be grounded if unused.
45 GPIO0 bidirectional General purpose digital I/O that may be used as DisplayPort HPD signal for Port B; tie to PP5V or ground when unused.
46 GPIO5 bidirectional General purpose digital I/O that may be used as an ADC input; tie to PP5V or ground when unused.
47 I2C3m_IRQ input I2C master interrupt, active low; connect to external voltage through a pull-up resistor, tie to PP5V or ground when unused, can be reconfigured to GPIO12.
48 I2C3m_SDA bidirectional I2C master serial data, open-drain; tie to pullup voltage through a resistor when used or unused.
49 GND power_in Thermal pad (GND) on the bottom of the package, connected to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(6x6)
Category Power Supply Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
PP5V input voltage PP5V 4.9 5.5 V 6
VIN_3V3 input voltage VIN_3V3 3 3.6 V 6
PA_VBUS, PB_VBUS input voltage Px_VBUS 4 22 V 6
VSYS input voltage VSYS 0 22 V 6
Ambient operating temperature TA -40 105 °C IPP_5Vx ≤ 1.5 A, IPP_5Vy ≤ 3.0 A, IPP_CABLEx ≤ 315 mA 6
Ambient operating temperature TA -40 85 °C IPP_5Vx ≤ 3.0 A, IPP_CABLEx ≤ 315 mA 6
Operating junction temperature TJ -40 125 °C 6
Output current from PP5V on Px_VBUS IO 3 A PA_VBUS, PB_VBUS 6
Abs max PP5V PP5V -0.3 6 V 5
Abs max VIN_3V3 VIN_3V3 -0.3 4 V 5
Abs max VSYS, PA_VBUS, PB_VBUS -0.3 28 V 5
Abs max Px_CCy -0.5 6 V 5
Abs max gate pins -0.3 40 V PA_GATE_VBUS, PA_GATE_VSYS, PB_GATE_VBUS, PB_GATE_VSYS 5
Operating junction temperature (abs max) TJ -40 175 °C 5
Storage temperature TSTG -55 150 °C 5
Junction-to-ambient thermal resistance RθJA 26.8 °C/W QFN (RSL) 48 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 15.4 °C/W 6
Junction-to-board thermal resistance RθJB 8.5 °C/W 7
VIN_3V3 UVLO rising VVIN3V3_UVLO 2.56 2.66 2.76 V rising, VPx_VBUS=0 7
VIN_3V3 UVLO falling VVIN3V3_UVLO 2.44 2.54 2.64 V falling, VPx_VBUS=0 7
Voltage on LDO_3V3 VLDO_3V3 2.7 3.4 3.6 V VVIN_3V3 = 0V, ILDO_3V3 ≤ 5 mA, VPA_VBUS ≥ 3.9V or VPB_VBUS ≥ 3.9V 7
Rdson VIN_3V3 to LDO_3V3 RLDO_3V3 1.5 Ω ILDO_3V3=50mA 7
Current into VIN_3V3 Active Source IVIN_3V3,ActSrc 4.5 12 mA Active Source mode: VPP5V=5.0V, VVIN_3V3=3.3V 7
Current into VIN_3V3 Active Sink IVIN_3V3,ActSnk 4.8 12 mA Active Sink mode, VVIN_3V3=3.3V 7
Current into VIN_3V3 Sleep IVIN_3V3,Sleep 67 µA Sleep mode: VPA_VBUS=0V, VPB_VBUS=0V, VVIN_3V3=3.3V, TJ ≤ 25 oC 7
PP5V to Px_VBUS resistance RPP_5V 37.7 41.5 mΩ ILOAD = 3 A, TJ≤25oC 8
PP5V to Px_VBUS resistance RPP_5V 37.7 57 mΩ ILOAD = 3 A, TJ≤125oC 8
Current limit setting 0 ILIM5V 1.15 1.36 A Configure to setting 0 8
Current limit setting 3 ILIM5V 3.04 3.58 A configure to setting 3 8
Current limit setting 4 ILIM5V 3.22 3.78 A configure to setting 4 8
Gate driver sourcing current IPx_GATE_ON 8.5 10 11.5 µA 0 ≤ VPx_GATE_VBUS-VPx_VBUS ≤ 6 V, 4 V ≤ VPx_VBUS ≤ 22 V 9
VBUS OVP threshold tolerance -5 5 % Tolernance of VOVP4RCP threshold 10
PP5V UVLO rising VPP5V_UVLO 3.9 4.1 4.3 V rising 10
PP5V UVLO falling VPP5V_UVLO 3.8 4 4.2 V falling 10
Rp current source USB Default IRpDef 64 80 96 µA 0 < VPx_CCy < 1.0 V, measure IPx_CCy 11
Rp current source 1.5A IRp1.5 166 180 194 µA 4.75 V < VPP5V < 5.5 V, 0 < VPx_CCy < 1.5 V 11
Rp current source 3.0A IRp3.0 304 330 356 µA 4.75 V < VPP5V < 5.5 V, 0 < VPx_CCy < 2.45 V 11
Rd pulldown resistance RSNK 4.1 6.1 kΩ 0.25 V ≤ VPx_CCy ≤ 2.1 V 11
Rdson of VCONN path RPP_CABLE 0.4 0.7 Ω VPP5V=5V, IL = 250 mA 12
VCONN current limit setting 0 ILIMVC 350 410 470 mA setting 0, VPP5V=5V, RL=10mΩ 12
Transmit high voltage VTXHI 1.05 1.125 1.2 V Standard External load 12
Thermal shutdown threshold TSD_MAIN 145 160 175 °C Temperature rising 13
ADC gain error GAIN_ERR -2.7 2.7 % 0.05V ≤ VADCINx ≤ 3.6V, VADCINx ≤ VLDO_3V3 13
ADC offset error VOS_ERR -4.1 4.1 mV 0.05V ≤ VADCINx ≤ 3.6V, VADCINx ≤ VLDO_3V3 13
GPIO internal pull-up GPIO_RPU 50 100 150 kΩ pull-up enabled 14
GPIO output low voltage GPIO_VOL 0.4 V VLDO_3V3 = 3.3V, IGPIOx=2mA 14
ESD HBM V(ESD) -1000 1000 V Human body model, all pins 5
ESD CDM V(ESD) -500 500 V Charged device model, all pins 5

CAD (KiCad official)

  • Symbol: TPS65994ADRSLR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps65994adrslr-etched.step / tps65994adrslr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65994adrslr.step / tps65994adrslr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 5b53d740e43da753, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF