component
TPS65632RTER
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65632RTER
Texas Instruments · Power Management Specialized - PMIC · WQFN-16-EP(3x3)
TPS65632RTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SWP1 | input | Boost converter 1 (VPOS) switch pin; absolute maximum rating is -0.3 V to 5 V with respect to GND. |
| 2 | PGND1 | power_in | Boost converter 1 power ground, to be connected to AGND and PGND2 through the exposed thermal pad. |
| 3 | OUTP1 | output | Boost converter 1 (VPOS) output, factory-fixed at 4.6 V; absolute maximum rating is -0.3 V to 5 V. |
| 4 | FBS | input | Boost converter 1 output sense input, to be connected directly to the positive terminal of the main output capacitor for highest accuracy; if floating or grounded, VPOS is sensed through OUTP1. |
| 5 | SELP2 | input | AVDD output voltage select: AVDD = 7.7 V when SELP2 is low (or left floating) and 5.8 V when high; absolute maximum rating is -0.3 V to 5.5 V. |
| 6 | CT | bidirectional | Capacitor connection that sets the VNEG transition time, with τ = 300 kΩ (typical CT pin resistance) × C(CT); absolute maximum rating is -0.3 V to 3.6 V. |
| 7 | AGND | power_in | Analog ground, to which the CT capacitor ground must be connected directly and which must be tied to PGND1, PGND2 and the exposed pad. |
| 8 | EN | input | Boost converter 2 (AVDD) enable; logic high minimum 1.2 V, logic low maximum 0.4 V, absolute maximum rating 5.5 V. |
| 9 | CTRL | input | Enables the device when pulled high (disables when low) and programs VNEG by counting rising edges, with -4.0 V default and a -1.4 V to -5.4 V range; absolute maximum rating is 5.5 V. |
| 10 | OUTN | output | Inverting buck-boost converter output (VNEG), with absolute limits of -6.0 V to 0.3 V. |
| 11 | SWN | bidirectional | Inverting buck-boost converter switch pin, with absolute limits of -6.5 V to 4.8 V. |
| 12 | PVIN | power_in | Inverting buck-boost converter power-stage supply; absolute maximum rating is -0.3 V to 5 V, and the device input supply range is 2.9 V to 4.5 V. |
| 13 | OUTP2 | output | Boost converter 2 (AVDD) output; absolute maximum rating is -0.3 V to 8.5 V. |
| 14 | PGND2 | power_in | Boost converter 2 power ground, to be connected to AGND and PGND1 through the exposed thermal pad. |
| 15 | SWP2 | input | Boost converter 2 (AVDD) switch pin; absolute maximum rating is -0.3 V to 12 V. |
| 16 | AVIN | power_in | Supply voltage pin for the device; absolute maximum rating is -0.3 V to 5 V, and the input supply range is 2.9 V to 4.5 V. |
| 17 | EP | power_in | Exposed thermal pad, to be connected to AGND, PGND1 and PGND2 and soldered to the PCB for thermal and mechanical performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16-EP(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| SWP1, OUTP1, FBS, PVIN, AVIN voltage | -0.3 | 5 | V | 4 | |||
| SWP2 voltage | -0.3 | 12 | V | 4 | |||
| OUTP2 voltage | -0.3 | 8.5 | V | 4 | |||
| OUTN voltage | -6 | 0.3 | V | 4 | |||
| SWN voltage | -6.5 | 4.8 | V | 4 | |||
| CTRL, EN, SELP2 voltage | -0.3 | 5.5 | V | 4 | |||
| CT voltage | -0.3 | 3.6 | V | 4 | |||
| Operating virtual junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input supply voltage range | VI | 2.9 | 3.7 | 4.5 | V | 4 | |
| Operating junction temperature | TJ | -40 | 85 | 125 | °C | 4 | |
| Input voltage range | VI | 2.9 | 3.7 | 4.5 | V | 5 | |
| Shutdown current | ISD | 0.25 | 5 | µA | CTRL = GND, EN = GND, sum of current flowing into AVIN and PVIN | 5 | |
| Under-voltage lockout threshold, falling | VUVLO | 1.8 | 2.1 | V | VI falling | 5 | |
| Under-voltage lockout threshold, rising | VUVLO | 2.1 | 2.5 | V | VI rising | 5 | |
| VPOS output voltage variation, 25°C to 85°C | VPOS | -0.5 | 0.5 | % | 25°C ≤ TA ≤ 85°C, No load | 5 | |
| VPOS output voltage variation, -30°C to 85°C | VPOS | -0.8 | 0.8 | % | -30°C ≤ TA ≤ 85°C, No load | 5 | |
| Switch current limit (boost 1) | ISW1 | 0.8 | 1 | 1.4 | A | Inductor valley current | 5 |
| Short-circuit threshold in operation (VPOS falling) | VSCP1 | 3.95 | 4.1 | 4.28 | V | VPOS falling | 5 |
| Output voltage sense threshold, increasing | VT | 200 | 300 | 550 | mV | V(OUTP1), V(FBS) increasing | 5 |
| Output voltage sense threshold, decreasing | VT | 100 | 200 | 450 | mV | V(OUTP1), V(FBS) decreasing | 5 |
| FBS pin pull-down resistance | R(FBS) | 2 | 4 | 6 | MΩ | 5 | |
| Discharge resistance (boost 1) | RDCHG1 | 10 | 30 | 70 | Ω | CTRL = GND, I(SWP1) = 1mA | 5 |
| VNEG output voltage range | VNEG | -5.4 | -1.4 | V | 5 | ||
| VNEG output voltage accuracy, 25°C to 85°C | VNEG | -50 | 50 | mV | 25°C ≤ TA ≤ 85°C, no load | 5 | |
| VNEG output voltage accuracy, -30°C to 85°C | VNEG | -60 | 60 | mV | -30°C ≤ TA ≤ 85°C, no load | 5 | |
| SWN switch current limit | ISW2 | 1.5 | 2.2 | 3 | A | VI = 2.9 V | 5 |
| Short circuit threshold in operation (voltage increase from nominal VNEG) | VSCP2 | 300 | 500 | 700 | mV | Voltage increase from nominal VNEG | 5 |
| Short circuit threshold in start up | VSCP2 | 180 | 200 | 230 | mV | start up | 5 |
| Discharge resistance (inverting buck-boost) | RDCHG2 | 130 | 150 | 170 | Ω | CTRL = GND, I(SWN) = 1 mA | 5 |
| AVDD output voltage accuracy, 25°C to 85°C | AVDD | -1 | 1 | % | 25°C ≤ TA ≤ 85°C, no load | 6 | |
| AVDD output voltage accuracy, -30°C to 85°C | AVDD | -1.3 | 1.3 | % | -30°C ≤ TA ≤ 85°C, no load | 6 | |
| Switch current limit (boost 2) | ILIM3 | 0.25 | 0.35 | 0.45 | A | Inductor valley current | 6 |
| Discharge resistance (boost 2) | RDCHG3 | 10 | 30 | 70 | Ω | EN = GND, I(SWP2) = 1 mA | 6 |
| Logic input high level voltage | VIH | 1.2 | V | 6 | |||
| Logic input low level voltage | VIL | 0.4 | V | 6 | |||
| Pull-down resistance (CTRL interface) | R | 150 | 400 | 860 | kΩ | 6 | |
| CT pin resistance | RCT | 150 | 300 | 500 | kΩ | 6 | |
| Initialization time | tINIT | 300 | 400 | µs | 6 | ||
| Data storage/accept time period | tSTORE | 30 | 80 | µs | 6 | ||
| Shutdown time period | tSDN | 30 | 80 | µs | 6 | ||
| Low-level pulse duration | tLOW | 2 | 10 | 25 | µs | 6 | |
| High-level pulse duration | tHIGH | 2 | 10 | 25 | µs | 6 | |
| Shutdown pulse duration | tOFF | 200 | µs | CTRL = low | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 42.9 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 44 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 14.2 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 0.6 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 14.1 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.3 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPS65632RTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps65632rter-etched.step/tps65632rter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65632rter.step/tps65632rter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
d873bac20b81c803, retrieved 2026-10-28, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).