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TPS65276VRHHR

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Texas Instruments DC-DC Converters, VQFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chiptps65276vrhhrfactory-2.0.0extractor-text

Verified TPS65276VRHHR

by Ray · last 6 Nov 2026 · 1 record · files match
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Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 37 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS65276VRHHR · VQFN-36-EP(6x6) · 37 pins
  • ✓copper: 37 copper pads, none touching another net
  • ✓datasheet: all 37 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C2071628, digikey 296-40889-2-ND, mouser 595-TPS65276VRHHR
  • ✓family: QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-y695iqwo/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 37 pins = 37 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 37 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps65276vrhhr.kicad_sym✓ tps65276vrhhr.kicad_mod✓ tps65276vrhhr.step
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TPS65276VRHHR

Texas Instruments · DC-DC Converters · VQFN-36-EP(6x6)

TPS65276VRHHR from Texas Instruments, in a VQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVIN2 power_in Power input supplying the power switches of converter 2.
2 PVIN2 power_in Power input supplying the power switches of converter 2.
3 ADDR input I2C address configuration pin; connect to low, high, or leave open to select the I2C slave address.
4 MODE input Operation mode control: ground selects forced PWM without current sharing, open selects pulse skipping mode at light load, and V7V selects forced PWM with current sharing for paralleled bucks.
5 V7V power_out Internal LDO output regulating to a typical 6.3 V, requiring a minimum 1-µF ceramic capacitor to power ground; the LDO current limit is 200 mA.
6 VIN power_in Power supply of the internal LDO and controllers, operating from 4.5 V to 18 V.
7 PVIN1 power_in Power input supplying the power switches of converter 1.
8 PVIN1 power_in Power input supplying the power switches of converter 1.
9 PGND1 power_in Power ground of Buck 1; place the input capacitor ground as close as possible to this pin.
10 PGND1 power_in Power ground of Buck 1; place the input capacitor ground as close as possible to this pin.
11 PGND1 power_in Power ground of Buck 1; place the input capacitor ground as close as possible to this pin.
12 SDA bidirectional I2C interface data pin.
13 SCL input I2C interface clock pin.
14 FB1 input Feedback sensing pin for the external feedback resistors of Buck 1, used to pre-set the output voltage before I2C VID selection is enabled.
15 VOUT1 input Buck 1 output voltage sensing pin; with I2C VID enabled the output is programmable from 0.68 V to 1.95 V in 10-mV steps.
16 BST1 passive Bootstrap capacitor connection between BST1 and LX1 that carries the gate drive voltage for the high-side MOSFET.
17 LX1 output Switching node of Buck 1.
18 LX1 output Switching node of Buck 1.
19 LX1 output Switching node of Buck 1.
20 SS1 input Soft-start and voltage tracking pin for Buck 1; an external capacitor sets the internal reference rise time.
21 COMP1 passive Error amplifier output and loop compensation pin for Buck 1.
22 ROSC passive Oscillator frequency programming pin; an external resistor sets the switching frequency from 200 kHz to 1.6 MHz, and an external clock can synchronize it.
23 AGND power_in Analog ground of the controllers.
24 COMP2 passive Error amplifier output and loop compensation pin for Buck 2; connect to ground in current sharing applications.
25 SS2 input Soft-start and voltage tracking pin for Buck 2; an external capacitor sets the internal reference rise time.
26 LX2 output Switching node of Buck 2.
27 LX2 output Switching node of Buck 2.
28 LX2 output Switching node of Buck 2.
29 BST2 passive Bootstrap capacitor connection between BST2 and LX2 that carries the gate drive voltage for the high-side MOSFET of Buck 2.
30 VOUT2 input Buck 2 output voltage sensing pin; with I2C VID enabled the output is programmable from 0.68 V to 1.95 V in 10-mV steps.
31 FB2 input Feedback sensing pin for the external feedback resistors of Buck 2, used to pre-set the output voltage before I2C VID selection is enabled.
32 EN1 input Enable pin for Buck 1; the input under-voltage lockout is adjusted with two resistors.
33 EN2 input Enable pin for Buck 2; the input under-voltage lockout is adjusted with two resistors.
34 PGND2 power_in Power ground of Buck 2; place the input capacitor ground as close as possible to this pin.
35 PGND2 power_in Power ground of Buck 2; place the input capacitor ground as close as possible to this pin.
36 PGND2 power_in Power ground of Buck 2; place the input capacitor ground as close as possible to this pin.
37 Exposed Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-36-EP(6x6)
Category Power Supply Chip
Pins 37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input operating voltage VIN 4.5 18 V 9
Ambient temperature TA -40 85 °C 9
Voltage range at VIN, PVIN1, PVIN2 VIN -0.3 20 V 8
Voltage range at LX1, LX2 (transient < 20 ns) LX -4.5 20 V maximum withstand voltage transient < 20 ns 8
Voltage at BST1, BST2 referenced to LX1, LX2 BST -0.3 7 V referenced to LX1, LX2 pin 8
Voltage at V7V, EN1, EN2, VOUT1, VOUT2, MODE V7V, EN1, EN2, VOUT1, VOUT2, MODE -0.3 7 V 8
Voltage at SS1, SS2, FB1, FB2, COMP1, COMP2 SS, FB, COMP -0.3 3 V 8
Voltage at SDA, SCL, ADDR, EN1, EN2, ROSC SDA, SCL, ADDR, EN, ROSC -0.3 7 V 8
Voltage at AGND, PGND1, PGND2 AGND, PGND -0.3 0.3 V 8
Operating virtual junction temperature range TJ -40 150 °C 8
Storage temperature range TSTG -55 150 °C 8
Input Voltage range VIN 4.5 18 V VIN1 and VIN2 9
Shutdown supply current IDDSDN 10 µA EN1 = EN2 = low 9
UVLO VIN under voltage lockout rising UVLO 4.25 4.5 V Rising VIN 9
UVLO VIN under voltage lockout falling UVLO 3.5 3.75 V Falling VIN 9
V7V LDO output V7V 6.1 6.3 6.5 V V7V load current = 0 A, VIN = 12 V 9
Enable threshold rising VENR 1.21 1.26 V 9
Enable threshold falling VENF 1.1 1.17 V 9
Switching frequency range FSW 200 1600 kHz 9
Switching frequency FSW 340 400 460 kHz ROSC = 100 kΩ (1%) 9
Clock sync minimum pulse width TSYNC_w 20 ns 9
Clock sync high threshold VSYNC_HI 2 V 9
Clock sync low threshold VSYNC_LO 0.8 V 9
Clock sync frequency range FSYNC 200 1600 kHz 9
Voltage reference Vref 0.594 0.6 0.606 V 0 A < IOUT1 < 6 A, 0 A < IOUT2 < 3.5 A 10
Output voltage step size VOUT1,2 8 10 12 mV VID 0x00, 0x7F 10
SDA, SCL input high voltage VIH 1.3 V 10
SDA, SCL input low voltage VIL 0.4 V 10
SDA, SCL input current II -10 10 µA SDA, SCL, VI = 0.4 V to 4.5 V 10
SDA output low voltage VOL 0.4 V SDA open drain, IOL = 4 mA 10
Maximum SCL clock frequency f(SCL) 400 kHz 10
Bus free time between a STOP and START condition tBUF 1.3 µs 10
Hold time (Repeated) START condition tHD_STA 0.6 µs 10
Setup time for STOP condition tSU_STO 0.6 µs 10
LOW period of the SCL clock tLOW 1.3 µs 10
HIGH period of the SCL clock tHIGH 0.6 µs 10
Setup time for a repeated START condition tSU_STA 0.6 µs 10
Data setup time tSU_DAT 0.1 µs 11
Data hold time tHD_DAT 0 0.9 µs 11
Rise time of SCL signal tRCL 300 ns Capacitance of one bus line (pF) 20+0.1CB 11
Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL1 300 ns Capacitance of one bus line (pF) 20+0.1CB 11
Fall time of SCL signal tFCL 300 ns Capacitance of one bus line (pF) 20+0.1CB 11
Rise time of SDA signal tRDA 300 ns Capacitance of one bus line (pF) 20+0.1CB 11
Fall time of SDA signal tFDA 300 ns Capacitance of one bus line (pF) 20+0.1CB 11
Capacitance of one bus line (SCL and SDA) CB 400 pF 11
Junction-to-ambient thermal resistance (RHH 36 pins) θJA 30.8 °C/W JEDEC high-K board, natural convection 8
Junction-to-case (top) thermal resistance (RHH 36 pins) θJCtop 18.8 °C/W 8
Junction-to-board thermal resistance (RHH 36 pins) θJB 6 °C/W 8
Junction-to-top characterization parameter (RHH 36 pins) ψJT 0.2 °C/W 8
Junction-to-board characterization parameter (RHH 36 pins) ψJB 6 °C/W 8
Junction-to-case (bottom) thermal resistance (RHH 36 pins) θJCbot 0.7 °C/W 8

CAD (KiCad official)

  • Symbol: TPS65276VRHHR
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: VQFN-36-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps65276vrhhr-etched.step / tps65276vrhhr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65276vrhhr.step / tps65276vrhhr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 6a12a26f9c6dc9f3, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF