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TPS65273VRHHR

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Texas Instruments DC-DC Converters, VQFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS65273VRHHR

Texas Instruments · DC-DC Converters · VQFN-36-EP(6x6)

TPS65273VRHHR from Texas Instruments, in a VQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVIN2 power_in Power input supplying the power switches of Buck 2, with an input operating range of 4.5 V to 18 V (absolute maximum 20 V).
2 PVIN2 power_in Power input supplying the power switches of Buck 2, with an input operating range of 4.5 V to 18 V (absolute maximum 20 V).
3 ADDR input I2C address configuration pin; connect to low, high, or leave open to select the I2C slave address (absolute maximum 7 V).
4 MODE input Operation mode control: ground selects forced PWM without current sharing, open selects pulse-skipping mode at light load, and V7V selects forced PWM with two-buck current sharing (absolute maximum 7 V).
5 V7V power_out Internal LDO output powering the internal driver and control circuits, regulated to a typical 6.3 V and requiring at least 1 µF ceramic decoupling to power ground (absolute maximum 7 V).
6 VIN power_in Supply input for the internal LDO and controllers, with an operating range of 4.5 V to 18 V.
7 PVIN1 power_in Power input supplying the power switches of Buck 1, with an input operating range of 4.5 V to 18 V (absolute maximum 20 V).
8 PVIN1 power_in Power input supplying the power switches of Buck 1, with an input operating range of 4.5 V to 18 V (absolute maximum 20 V).
9 PGND1 power_in Power ground of Buck 1; place the input capacitor ground return as close as possible to this pin.
10 PGND1 power_in Power ground of Buck 1; place the input capacitor ground return as close as possible to this pin.
11 PGND1 power_in Power ground of Buck 1; place the input capacitor ground return as close as possible to this pin.
12 SDA bidirectional I2C interface data pin (absolute maximum 7 V).
13 SCL input I2C interface clock pin (absolute maximum 7 V).
14 FB1 input Feedback sense pin for the Buck 1 external resistor divider that pre-sets the output voltage before I2C VID is enabled, referenced to 0.6 V (absolute maximum 3 V).
15 VOUT1 input Buck 1 output voltage sense pin; with I2C VID enabled the output is programmable from 0.68 V to 1.95 V in 10-mV steps (absolute maximum 7 V).
16 BST1 passive Bootstrap capacitor connection between BST1 and LX1 that supplies the high-side MOSFET gate drive (absolute maximum 7 V referenced to LX1).
17 LX1 output Buck 1 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
18 LX1 output Buck 1 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
19 LX1 output Buck 1 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
20 SS1 passive Soft-start and voltage tracking pin for Buck 1; an external capacitor sets the reference rise time and the pin can override the internal reference for tracking (absolute maximum 3 V).
21 COMP1 passive Error amplifier output and loop compensation pin for Buck 1 (absolute maximum 3 V).
22 ROSC input Oscillator frequency pin; an external resistor sets the switching frequency (100 kΩ gives 340 to 460 kHz, 400 kHz typical), and an external clock can synchronize the oscillator (absolute maximum 7 V).
23 AGND power_in Analog ground of the controllers; connect at one point to the (-) terminal of the V7V bypass capacitor together with power ground.
24 COMP2 passive Error amplifier output and loop compensation pin for Buck 2; connect to ground in current sharing application (absolute maximum 3 V).
25 SS2 passive Soft-start and voltage tracking pin for Buck 2; connect to ground in current sharing application (absolute maximum 3 V).
26 LX2 output Buck 2 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
27 LX2 output Buck 2 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
28 LX2 output Buck 2 switching node; withstands -4.5 V to 20 V (transients under 20 ns).
29 BST2 passive Bootstrap capacitor connection between BST2 and LX2 that supplies the Buck 2 high-side MOSFET gate drive (absolute maximum 7 V referenced to LX2).
30 VOUT2 input Buck 2 output voltage sense pin; with I2C VID enabled the output is programmable from 0.68 V to 1.95 V in 10-mV steps, and it connects to ground in current sharing application (absolute maximum 7 V).
31 FB2 input Feedback sense pin for the Buck 2 external resistor divider that pre-sets the output voltage before I2C VID is enabled, referenced to 0.6 V (absolute maximum 3 V).
32 EN1 input Buck 1 enable pin; input under-voltage lockout is adjustable with two resistors and the pin may be left floating for automatic start (absolute maximum 7 V).
33 EN2 input Buck 2 enable pin; input under-voltage lockout is adjustable with two resistors and the pin may be left floating for automatic start (absolute maximum 7 V).
34 PGND2 power_in Power ground of Buck 2; place the input capacitor ground return as close as possible to this pin.
35 PGND2 power_in Power ground of Buck 2; place the input capacitor ground return as close as possible to this pin.
36 PGND2 power_in Power ground of Buck 2; place the input capacitor ground return as close as possible to this pin.
37 Exposed Thermal Pad power_in Exposed thermal pad, connected to power ground; solder to the board with as many vias as possible for heat dissipation, and no electrical signal is bonded to it inside the package.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-36-EP(6x6)
Category Power Management (PMIC)
Pins 37

CAD (KiCad official)

  • Symbol: TPS65273VRHHR
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: VQFN-36-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps65273vrhhr-etched.step / tps65273vrhhr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65273vrhhr.step / tps65273vrhhr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (49 pp, sha256 e0172c0cd4d6d465, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF