component
TPS65266RHBT
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| README.md | 25d ago |
| tps65266rhbt-etched.glb | 29d ago |
| tps65266rhbt-etched.step | 29d ago |
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TPS65266RHBT
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65266RHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground pin; the datasheet gives no separate limits for this pin, and analog ground must be routed separately from high-current power grounds. |
| 2 | AGND | power_in | Analog ground pin; the datasheet gives no separate limits for this pin, and analog ground must be routed separately from high-current power grounds. |
| 3 | AGND | power_in | Analog ground pin; the datasheet gives no separate limits for this pin, and analog ground must be routed separately from high-current power grounds. |
| 4 | PGOOD | output | Open-drain power-good output that asserts low if a buck output is outside its regulation range due to thermal shutdown, overcurrent, undervoltage, or ENx low. |
| 5 | VINQ | power_in | Input voltage for the converter controller and reference bias (2.7 V to 6.5 V recommended); TI recommends a 1-µF capacitor from this pin to analog ground placed as near as possible to the pin. |
| 6 | FB2 | input | Kelvin-sensing feedback input for the buck2 output voltage, connected to the buck2 feedback resistor divider. |
| 7 | COMP2 | passive | Error-amplifier output and loop-compensation pin for buck2, compensated with a series resistor and capacitor in peak-current PWM mode. |
| 8 | SS2 | passive | Soft-start and tracking input for buck2 with an internal 5.5-µA pullup; the soft-start time is set by a capacitor from this pin to ground. |
| 9 | BST2 | power_out | Bootstrap supply for the buck2 high-side gate driver; connect a 47-nF (recommended) capacitor from BST2 to LX2. |
| 10 | LX2 | output | Switching node for buck2 connecting to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the VIN2 voltage. |
| 11 | PGND2 | power_in | Power ground for buck2, to be connected as close as practical to the negative terminal of the VIN2 input ceramic capacitor. |
| 12 | VIN2 | power_in | Input power supply for buck2, to be connected as close as practical to the positive terminal of an input ceramic capacitor (10 µF suggested). |
| 13 | VIN3 | power_in | Input power supply for buck3, to be connected as close as practical to the positive terminal of an input ceramic capacitor (10 µF suggested). |
| 14 | PGND3 | power_in | Power ground for buck3, to be connected as close as practical to the negative terminal of the VIN3 input ceramic capacitor. |
| 15 | LX3 | output | Switching node for buck3 connecting to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the VIN3 voltage. |
| 16 | BST3 | power_out | Bootstrap supply for the buck3 high-side gate driver; connect a 47-nF (recommended) capacitor from BST3 to LX3. |
| 17 | SS3 | passive | Soft-start and tracking input for buck3 with an internal 5.5-µA pullup; the soft-start time is set by a capacitor from this pin to ground. |
| 18 | COMP3 | passive | Error-amplifier output and loop-compensation pin for buck3, compensated with a series resistor and capacitor in peak-current PWM mode. |
| 19 | FB3 | input | Kelvin-sensing feedback input for the buck3 output voltage, connected to the buck3 feedback resistor divider. |
| 20 | ROSC | passive | Oscillator frequency programming pin; an external resistor connected here sets the switching frequency. |
| 21 | AGND | power_in | Analog ground common to the buck controllers and other analog circuits, to be routed separately from high-current power grounds to the negative terminal of the VINQ bypass capacitor. |
| 22 | FB1 | input | Kelvin-sensing feedback input for the buck1 output voltage, connected to the buck1 feedback resistor divider. |
| 23 | COMP1 | passive | Error-amplifier output and loop-compensation pin for buck1, compensated with a series resistor and capacitor in peak-current PWM mode. |
| 24 | SS1 | passive | Soft-start and tracking input for buck1 with an internal 5.5-µA pullup; the soft-start time is set by a capacitor from this pin to ground. |
| 25 | BST1 | power_out | Bootstrap supply for the buck1 high-side gate driver; connect a 47-nF (recommended) capacitor from BST1 to LX1. |
| 26 | LX1 | output | Switching node for buck1 connecting to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the VIN1 voltage. |
| 27 | PGND1 | power_in | Power ground for buck1, to be connected as close as practical to the negative terminal of the VIN1 input ceramic capacitor. |
| 28 | VIN1 | power_in | Input power supply for buck1, to be connected as close as practical to the positive terminal of an input ceramic capacitor (10 µF suggested). |
| 29 | EN1 | input | Enable for buck1; float to enable, and a resistor divider can be used to adjust its input undervoltage lockout. |
| 30 | EN2 | input | Enable for buck2; float to enable, and a resistor divider can be used to adjust its input undervoltage lockout. |
| 31 | EN3 | input | Enable for buck3; float to enable, and a resistor divider can be used to adjust its input undervoltage lockout. |
| 32 | GND | power_in | Ground pin. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN1, VIN2, VIN3, VINQ | -0.3 | 7 | V | 5 | |||
| LX1, LX2, LX3 | -1 | 7 | V | maximum withstand voltage transient <20 ns | 5 | ||
| BST1, BST2, BST3 | -0.3 | 7 | V | referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| EN1, EN2, EN3, PGOOD | -0.3 | 7 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3, ROSC | -0.3 | 3.6 | V | 5 | |||
| AGND, PGND1, PGND2, PGND3 | -0.3 | 0.3 | V | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| VIN1, VIN2, VIN3, VINQ | 2.7 | 6.5 | V | 5 | |||
| LX1, LX2, LX3 | -0.8 | 6.5 | V | maximum withstand voltage transient <20 ns | 5 | ||
| BST1, BST2, BST3 | -0.1 | 6.5 | V | referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| EN1, EN2, EN3, PGOOD | -0.1 | 6.5 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3, ROSC | -0.1 | 3 | V | 5 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 34.2 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 27.5 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 8.3 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 0.4 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 8.3 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.8 | °C/W | 5 | |||
| Input voltage range | VIN | 2.7 | 6.5 | V | 6 | ||
| UVLO VIN undervoltage lockout | UVLO | 2.35 | 2.45 | 2.6 | V | VIN rising | 6 |
| UVLO VIN undervoltage lockout | UVLO | 2.15 | 2.25 | 2.35 | V | VIN falling | 6 |
| Soft-start charging current | ISSX | 4.5 | 5.5 | 6.5 | µA | 6 | |
| Buck1 peak inductor current limit | ILIMIT1 | 3.9 | 4.6 | 5.3 | A | 6 | |
| Buck2/3 peak inductor current limit | ILIMIT2/3 | 2.5 | 3.1 | 3.7 | A | 6 | |
| EN1/2/3 pullup current | IENX1 | 1.8 | 2.1 | 2.4 | µA | ENx = 1 V | 6 |
| Feedback voltage | VFB | 0.594 | 0.6 | 0.606 | V | VCOMP = 1.2 V | 6 |
| Switching frequency | FSW | 920 | 1000 | 1080 | kHz | ROSC = 51.1 kΩ | 7 |
| Switching frequency range | FSW_range | 250 | 2400 | kHz | 7 | ||
| Clock sync frequency range | FSYNC | 250 | 2400 | kHz | 7 |
CAD (KiCad official)
- Symbol:
TPS65266RHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65266rhbt-etched.step/tps65266rhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65266rhbt.step/tps65266rhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
76c5a2fb9d90a942, retrieved 2026-10-12, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).