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TPS65262RHBR

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Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS65262RHBR

Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)

TPS65262RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LVIN2 power_in Input power supply for LDO2, to be connected as close as possible to the (+) terminal of an input ceramic capacitor (suggest 1 µF).
2 LOUT2 power_out LDO2 output, to be connected as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
3 LFB2 input Feedback Kelvin sensing pin for LDO2 output voltage, connected to the LDO2 resistor divider.
4 LEN2 input Enable for LDO2; float to enable.
5 PGOOD output Open-drain output that asserts low if the output voltage of any buck is beyond regulation range due to thermal shutdown, overcurrent, undervoltage, or ENx shut down.
6 MODE input When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.
7 FB2 input Feedback Kelvin sensing pin for buck2 output voltage, connected to the buck2 resistor divider.
8 EN2 input Enable for buck2; float to enable, and can be used with a resistor divider to adjust the input undervoltage lockout of buck2.
9 BST2 passive Boot strapped supply to the high side floating gate driver in Buck2; connect a capacitor (recommend 47 nF) from BST2 to LX2.
10 LX2 output Switching node connection to the inductor and bootstrap capacitor for Buck2, swinging from a diode voltage below ground up to VIN2 voltage.
11 PGND2 power_in Power ground of Buck2, connected as close as possible to the (-) terminal of the VIN2 input ceramic capacitor.
12 VIN2 power_in Input power supply for Buck2, connected as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
13 VIN3 power_in Input power supply for Buck3, connected as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
14 PGND3 power_in Power ground of Buck3, connected as close as possible to the (-) terminal of the VIN3 input ceramic capacitor.
15 LX3 output Switching node connection to the inductor and bootstrap capacitor for Buck3, swinging from a diode voltage below ground up to VIN3 voltage.
16 BST3 passive Boot strapped supply to the high side floating gate driver in Buck3; connect a capacitor (recommend 47 nF) from BST3 to LX3.
17 EN3 input Enable for Buck3; float to enable, and can be used with a resistor divider to adjust the input undervoltage lockout of Buck3.
18 FB3 input Feedback Kelvin sensing pin for buck3 output voltage, connected to the Buck3 resistor divider.
19 AGND power_in Analog ground common to buck controllers and other analog circuits, routed separately from high current power grounds to the (-) terminal of the VIN bypass capacitor.
20 V7V power_out Internal LDO for gate driver and internal controller; connect a 10-µF capacitor from the pin to power ground.
21 COMP1 passive Error amplifier output and loop compensation pin for Buck1; connect a series resistor and capacitor to compensate the peak current PWM mode control loop.
22 SS1 passive Soft-start and tracking input for Buck1 with an internal 5-µA pullup current source; soft-start time is programmed with a capacitor to ground.
23 FB1 input Feedback Kelvin sensing pin for Buck1 output voltage, connected to the Buck1 resistor divider.
24 EN1 input Enable for Buck1; float to enable, and can be used with a resistor divider to adjust the input undervoltage lockout of Buck1.
25 BST1 passive Boot strapped supply to the high side floating gate driver in buck1; connect a capacitor (recommend 47 nF) from BST1 to LX1.
26 LX1 output Switching node connection to the inductor and bootstrap capacitor for buck1, swinging from a diode voltage below ground up to VIN1 voltage.
27 PGND1 power_in Power ground of buck1, connected as close as possible to the (-) terminal of the VIN1 input ceramic capacitor.
28 VIN1 power_in Input power supply for buck1, connected as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
29 LEN1 input Enable for LDO1; float to enable.
30 LFB1 input Feedback Kelvin sensing pin for LDO1 output voltage, connected to the LDO1 resistor divider.
31 LOUT1 power_out LDO1 output, to be connected as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
32 LVIN1 power_in Input power supply for LDO1, connected as close as possible to the (+) terminal of an input ceramic capacitor (suggest 1 µF).
33 PAD passive Exposed thermal pad with no electrical signal down bonded inside the IC; must be soldered to the PCB for optimal thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Power Supply Chip
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 4.5 18 V VIN1, VIN2, VIN3 5
Operating ambient temperature TA -40 85 °C 5
Operating junction temperature TJ -40 125 °C 5
LDO pins voltage LOUT1, LOUT2, LVIN1, LVIN2 -0.1 18 V 5
Abs max VIN1/2/3, LVIN1/2 VIN -0.3 20 V VIN1, VIN2, VIN3, LVIN1, LVIN2 5
Abs max LX LX -1 20 V LX1, LX2, LX3 (transient <20 ns) 5
Abs max BST to LX BST -0.3 7 V referenced to LX 5
Abs max logic pins -0.3 7 V MODE, LEN1, LEN2, EN1, EN2, EN3, PGOOD, V7V 5
Abs max LOUT LOUT1, LOUT2 -0.3 7 V 5
Abs max FB/COMP/SS -0.3 3.6 V FB1, FB2, FB3, LFB1, LFB2, COMP1, SS1 5
Abs max ground pins -0.3 0.3 V AGND, PGND1, PGND2, PGND3 5
Storage temperature Tstg -55 150 °C 5
Junction-to-ambient thermal resistance RθJA 32 °C/W RHB 32 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 24.2 °C/W 5
Junction-to-board thermal resistance RθJB 6.4 °C/W 5
UVLO rising UVLO 4 4.25 4.5 V VIN rising 7
UVLO falling UVLO 3.5 3.75 4 V VIN falling 7
Shutdown supply current IDDSDN 12 µA EN1 = EN2 = EN3 = MODE = LEN1 = LEN2 = 0 V 7
V7V LDO output voltage V7V 6 6.3 6.6 V V7V load current = 0 A 7
Feedback voltage VFB 0.595 0.6 0.605 V VCOMP = 1.2 V, TJ = 25°C 7
Feedback voltage VFB 0.594 0.6 0.606 V VCOMP = 1.2 V, TJ = -40°C to 125°C 7
Buck1 soft start charging current ISS1 4.3 5 6 µA 7
Minimum on time TON_MIN 80 100 ns 7
Buck1 peak inductor current limit ILIMIT1 4.4 5.1 6.06 A 7
Buck2/3 peak inductor current limit ILIMIT2/3 1.8 2.4 3 A 7
Switching frequency ƒSW 570 600 630 kHz 8
LDO1 voltage reference VLDOFB1 0.594 0.6 0.606 V load current = 10 mA, VIN = 12 V 8
LDO2 voltage reference VLDOFB2 0.594 0.6 0.606 V load current = 10 mA, VIN = 12 V 8
LDO1 current limit Imax_LDO1 240 330 mA 8
LDO2 current limit Imax_LDO2 120 180 mA 8
LDO1 input voltage range VINLDO1 1.3 18 V 8
LDO2 input voltage range VINLDO2 1.3 18 V 8
LDO1 output voltage range VOUTLDO1 1 5.5 V load current = 200 mA, VIN = 12 V 8
LDO2 output voltage range VOUTLDO2 1 5.5 V load current = 100 mA, VIN = 12 V 8
Input quiescent current without switching IDDQ_NSW 790 µA EN1 = EN2 = EN3 = 5V, FB1 = FB2 = FB3 = 0.8 V, LEN1 = LEN2 = 0 V 7
Thermal protection trip point TTRIP_OTP 160 °C Temperature rising 9
ESD HBM V(ESD) -2000 2000 V HBM, all pins 5
ESD CDM V(ESD) -500 500 V CDM, all pins 5

CAD (KiCad official)

  • Symbol: TPS65262RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps65262rhbr-etched.step / tps65262rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65262rhbr.step / tps65262rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 c80241ba1182adda, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF