component
TPS65261RHBR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownTPS65261RHBR
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65261RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN3 | input | Enable pin for buck3; float to enable or configure input undervoltage lockout with external resistor divider; operating range -0.1V to 6.3V, typical rising threshold 1.26V |
| 2 | PGOOD | output | Open-drain power good output; asserts low when any buck output is out of regulation (±2.5%), thermal shutdown active, overcurrent condition exists, or enable pin low; max sink 1mA at 0.4V |
| 3 | RESET | output | Open-drain power failure output signal; asserts low when VDIV input drops below 1.23V threshold for power failure detection; deglitch time 12-16 cycles |
| 4 | MODE | input | Mode select input; when high, enables automatic power-up/power-down sequencing based on EN1/EN2/EN3 states; when low, enables independent enable pin control; operating range -0.1V to 6.3V |
| 5 | V7V | power_out | Internal LDO output supplying gate drivers and internal logic; 6.3V typical (6.0V to 6.6V range), maximum current 175mA; requires 10µF ceramic capacitor to power ground |
| 6 | FB2 | input | Feedback Kelvin sensing pin for buck2 output voltage regulation; connect to resistor divider network for output voltage setting; operating range -0.1V to 3V |
| 7 | COMP2 | output | Error amplifier output for buck2 loop compensation; transconductance 300µS; connect series R and C for control loop compensation in peak current mode; operating range -0.1V to 3V |
| 8 | SS2 | input | Soft-start and tracking input for buck2 with internal 5µA pullup current source; connect capacitor to ground to program soft-start time; operating range -0.1V to 3V |
| 9 | BST2 | power_in | Bootstrap supply for buck2 high-side gate driver; connect 47nF ceramic capacitor between BST2 and LX2 pins; operating range -0.3V to 7V referenced to LX2 |
| 10 | LX2 | output | Buck2 switching node connected to external inductor and bootstrap capacitor; voltage swings from -0.8V (maximum withstand) to PVIN2 voltage (maximum 18V); high di/dt node requiring careful PCB layout |
| 11 | PGND2 | power_in | Buck2 power ground connection; connect as close as practical to negative terminal of PVIN2 input ceramic capacitor to minimize inductance |
| 12 | PVIN2 | power_in | Buck2 input power supply; operating range 4.5V to 18V; connect as close as practical to positive terminal of 10µF minimum input ceramic capacitor with clean voltage path |
| 13 | PVIN3 | power_in | Buck3 input power supply; operating range 4.5V to 18V; connect as close as practical to positive terminal of 10µF minimum input ceramic capacitor with clean voltage path |
| 14 | PGND3 | power_in | Buck3 power ground connection; connect as close as practical to negative terminal of PVIN3 input ceramic capacitor to minimize inductance |
| 15 | LX3 | output | Buck3 switching node connected to external inductor and bootstrap capacitor; voltage swings from -0.8V (maximum withstand) to PVIN3 voltage (maximum 18V); high di/dt node requiring careful PCB layout |
| 16 | BST3 | power_in | Bootstrap supply for buck3 high-side gate driver; connect 47nF ceramic capacitor between BST3 and LX3 pins; operating range -0.3V to 7V referenced to LX3 |
| 17 | SS3 | input | Soft-start and tracking input for buck3 with internal 5µA pullup current source; connect capacitor to ground to program soft-start time; operating range -0.1V to 3V |
| 18 | COMP3 | output | Error amplifier output for buck3 loop compensation; transconductance 300µS; connect series R and C for control loop compensation in peak current mode; operating range -0.1V to 3V |
| 19 | FB3 | input | Feedback Kelvin sensing pin for buck3 output voltage regulation; connect to resistor divider network for output voltage setting; operating range -0.1V to 3V |
| 20 | ROSC | input | Oscillator frequency programmable pin; connect external resistor to ground to set switching frequency from 250kHz to 2MHz; operating range -0.1V to 3V |
| 21 | AGND | power_in | Analog ground for buck controllers and analog signal circuits; route separately from high current power grounds to negative terminal of VIN bypass capacitor to minimize noise coupling |
| 22 | FB1 | input | Feedback Kelvin sensing pin for buck1 output voltage regulation; connect to resistor divider network for output voltage setting; operating range -0.1V to 3V |
| 23 | COMP1 | output | Error amplifier output for buck1 loop compensation; transconductance 300µS; connect series R and C for control loop compensation in peak current mode; operating range -0.1V to 3V |
| 24 | SS1 | input | Soft-start and tracking input for buck1 with internal 5µA pullup current source; connect capacitor to ground to program soft-start time; operating range -0.1V to 3V |
| 25 | BST1 | power_in | Bootstrap supply for buck1 high-side gate driver; connect 47nF ceramic capacitor between BST1 and LX1 pins; operating range -0.3V to 7V referenced to LX1 |
| 26 | LX1 | output | Buck1 switching node connected to external inductor and bootstrap capacitor; voltage swings from -0.8V (maximum withstand) to PVIN1 voltage (maximum 18V); high di/dt node requiring careful PCB layout and 180° phase shift from buck2/3 clocks |
| 27 | PGND1 | power_in | Buck1 power ground connection; connect as close as practical to negative terminal of PVIN1 input ceramic capacitor to minimize inductance |
| 28 | PVIN1 | power_in | Buck1 input power supply; operating range 4.5V to 18V; connect as close as practical to positive terminal of 10µF minimum input ceramic capacitor with clean voltage path |
| 29 | VIN | power_in | Buck controller power supply for internal logic and bias circuits; operating range 4.5V to 18V; UVLO thresholds: rising 4.25V typical, falling 3.75V typical, hysteresis 500mV |
| 30 | VDIV | input | Input voltage threshold for power failure detection; external resistor divider sets detection threshold to 1.23V typical; 1µA pullup current provides threshold hysteresis; operating range -0.1V to 6.3V |
| 31 | EN1 | input | Enable pin for buck1; float to enable or configure input undervoltage lockout with external resistor divider; operating range -0.1V to 6.3V, typical rising threshold 1.26V |
| 32 | EN2 | input | Enable pin for buck2; float to enable or configure input undervoltage lockout with external resistor divider; operating range -0.1V to 6.3V, typical rising threshold 1.26V |
| 33 | Thermal Pad | passive | Exposed thermal pad for junction-to-board heat dissipation; no internal electrical wire bond to die; must be soldered to PCB ground plane for optimal thermal performance |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
TPS65261RHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65261rhbr-etched.step/tps65261rhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65261rhbr.step/tps65261rhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
304396ee72bd117c, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).