component
TPS65261-1RHBR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1h ago |
| viewers | 1h ago |
| package.json | 1h ago |
| page.json | 1h ago |
| README.md | 1h ago |
| tps65261-1rhbr-etched.glb | 1h ago |
| tps65261-1rhbr-etched.step | 1h ago |
| tps65261-1rhbr-hero.glb | 1h ago |
| tps65261-1rhbr-hero.overlay.json | 1h ago |
| tps65261-1rhbr.glb | 1h ago |
| tps65261-1rhbr.kicad_mod | 1h ago |
| tps65261-1rhbr.kicad_sym | 1h ago |
| tps65261-1rhbr.lbr | 1h ago |
| tps65261-1rhbr.step | 1h ago |
| verification.json | 1h ago |
TPS65261-1RHBR
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65261-1RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN3 | input | Enable for buck3; float to enable, and a resistor divider can set the buck3 input undervoltage lockout. |
| 2 | PGOOD | output | Open-drain output that asserts low if any buck output is out of regulation due to thermal shutdown, overcurrent, undervoltage or ENx shutdown. |
| 3 | RESET | output | Open-drain power failure output signal. |
| 4 | MODE | input | When high, provides an automatic power-up/power-down sequence according to the states of EN1, EN2 and EN3. |
| 5 | V7V | power_out | Internal LDO output for the gate driver and internal controller; connect a 10-µF capacitor from this pin to power ground. |
| 6 | FB2 | input | Feedback Kelvin sensing pin for the buck2 output voltage; connect to the buck2 resistor divider. |
| 7 | COMP2 | passive | Error amplifier output and loop compensation pin for buck2; connect a series resistor and capacitor. |
| 8 | SS2 | passive | Soft-start and tracking input for buck2 with an internal 5-µA pullup; soft-start time is set by a capacitor to ground. |
| 9 | BST2 | power_out | Bootstrap supply for the buck2 high-side gate driver; connect a capacitor (recommend 47 nF) from BST2 to LX2. |
| 10 | LX2 | output | Buck2 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN2 voltage. |
| 11 | PGND2 | power_in | Power ground for buck2; place as close as practical to the negative terminal of the VIN2 input ceramic capacitor. |
| 12 | PVIN2 | power_in | Input power supply for buck2; place as close as practical to the positive terminal of an input ceramic capacitor (suggested 10 µF). |
| 13 | PVIN3 | power_in | Input power supply for buck3; place as close as practical to the positive terminal of an input ceramic capacitor (suggested 10 µF). |
| 14 | PGND3 | power_in | Power ground for buck3; place as close as practical to the negative terminal of the VIN3 input ceramic capacitor. |
| 15 | LX3 | output | Buck3 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN3 voltage. |
| 16 | BST3 | power_out | Bootstrap supply for the buck3 high-side gate driver; connect a capacitor (recommend 47 nF) from BST3 to LX3. |
| 17 | SS3 | passive | Soft-start and tracking input for buck3 with an internal 5-µA pullup; soft-start time is set by a capacitor to ground. |
| 18 | COMP3 | passive | Error amplifier output and loop compensation pin for buck3; connect a series resistor and capacitor. |
| 19 | FB3 | input | Feedback Kelvin sensing pin for the buck3 output voltage; connect to the buck3 resistor divider. |
| 20 | ROSC | passive | Oscillator frequency programming pin; an external resistor sets the switching frequency between 250 kHz and 2 MHz. |
| 21 | AGND | power_in | Analog ground common to the buck controllers and analog circuits; route separately from high-current power grounds to the negative terminal of the VIN bypass capacitor. |
| 22 | FB1 | input | Feedback Kelvin sensing pin for the buck1 output voltage; connect to the buck1 resistor divider. |
| 23 | COMP1 | passive | Error amplifier output and loop compensation pin for buck1; connect a series resistor and capacitor. |
| 24 | SS1 | passive | Soft-start and tracking input for buck1 with an internal 5-µA pullup; soft-start time is set by a capacitor to ground. |
| 25 | BST1 | power_out | Bootstrap supply for the buck1 high-side gate driver; connect a capacitor (recommend 47 nF) from BST1 to LX1. |
| 26 | LX1 | output | Buck1 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN1 voltage. |
| 27 | PGND1 | power_in | Power ground for buck1; place as close as practical to the negative terminal of the VIN1 input ceramic capacitor. |
| 28 | PVIN1 | power_in | Input power supply for buck1; place as close as practical to the positive terminal of an input ceramic capacitor (suggested 10 µF). |
| 29 | VIN | power_in | Buck controller power supply input; recommended operating range is 4.5 V to 18 V. |
| 30 | VDIV | input | Input voltage threshold for power failure detection of the input voltage. |
| 31 | EN1 | input | Enable for buck1; float to enable, and a resistor divider can set the buck1 input undervoltage lockout. |
| 32 | EN2 | input | Enable for buck2; float to enable, and a resistor divider can set the buck2 input undervoltage lockout. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| PVIN1, PVIN2, PVIN3, VIN input voltage | -0.3 | 20 | V | 5 | |||
| LX1, LX2, LX3 switch node voltage | -1 | 20 | V | Maximum withstand voltage transient < 20 ns | 5 | ||
| BST1, BST2, BST3 boot voltage | -0.3 | 7 | V | referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV voltage | -0.3 | 7 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3, ROSC voltage | -0.3 | 3.6 | V | 5 | |||
| AGND, PGND1, PGND2, PGND3 voltage | -0.3 | 0.3 | V | 5 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 5 | ||
| PVIN1, PVIN2, PVIN3, VIN input voltage range | 4.5 | 18 | V | 5 | |||
| LX1, LX2, LX3 switch node voltage | -0.8 | 18 | V | Maximum withstand voltage transient < 20 ns | 5 | ||
| BST1, BST2, BST3 boot voltage | -0.1 | 6.8 | V | referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV voltage | -0.1 | 6.3 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3, ROSC voltage | -0.1 | 3 | V | 5 | |||
| Operating ambient temperature | TA | -40 | 85 | °C | Operating junction temperature | 5 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| VIN input voltage range | 4.5 | 18 | V | 6 | |||
| VIN undervoltage lockout, rising | UVLO | 4 | 4.25 | 4.5 | V | VIN rising | 6 |
| VIN undervoltage lockout, falling | UVLO | 3.5 | 3.75 | 4 | V | VIN falling | 6 |
| V7V LDO output voltage | V7V | 6 | 6.3 | 6.6 | V | V7V load current = 0 A | 6 |
| Feedback voltage | VFB | 0.596 | 0.6 | 0.605 | V | VCOMP = 1.2 V, TJ = 25°C | 6 |
| Feedback voltage | VFB | 0.594 | 0.6 | 0.606 | V | VCOMP = 1.2 V, TJ = -40°C to 125°C | 6 |
| Soft start charging current | ISSX | 4.3 | 5 | 6 | µA | 6 | |
| Buck1 peak inductor current limit | ILIMIT1 | 4.33 | 5.1 | 6.02 | A | 6 | |
| Buck2/3 peak inductor current limit | ILIMIT2/3 | 2.6 | 3.1 | 3.73 | A | 6 | |
| VDIV threshold | VDIVth | 1.18 | 1.23 | 1.26 | V | 7 | |
| RESET deglitch on the falling edge | Tdeglitch_F | 12 | 14 | 16 | cycles | 7 | |
| Switching frequency | FSW | 560 | 600 | 640 | kHz | ROSC = 73.2 kΩ | 7 |
| Switching frequency range | FSW_range | 250 | 2000 | kHz | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 31.6 | °C/W | RHB (32 pins) | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 23.4 | °C/W | RHB (32 pins) | 5 | ||
| Junction-to-board thermal resistance | RθJB | 6.1 | °C/W | RHB (32 pins) | 5 | ||
| Junction-to-top characterization parameter | ψJT | 0.2 | °C/W | RHB (32 pins) | 5 | ||
| Junction-to-board characterization parameter | ψJB | 6.1 | °C/W | RHB (32 pins) | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.9 | °C/W | RHB (32 pins) | 5 |
CAD (KiCad official)
- Symbol:
TPS65261-1RHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65261-1rhbr-etched.step/tps65261-1rhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65261-1rhbr.step/tps65261-1rhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
1f24f24dc34c30ef, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).