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TPS6522053RHBR

Public Made by Adom

by adom

Texas Instruments Power Management - Specialized, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS6522053RHBR

Texas Instruments · Power Management - Specialized · VQFN-32(5x5)

TPS6522053RHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB_B1 input Feedback input for Buck1; connect to Buck1 output filter, nominal output voltage configured in EEPROM.
2 LX_B1_1 passive Switch pin for Buck1; connect one side of the Buck1 inductor to this pin.
3 LX_B1_2 passive 2nd switch pin for Buck1; connect one side of the Buck1 inductor and tie to LX_B1_1.
4 PVIN_B1_1 power_in Power input for Buck1; bypass to ground with 4.7 µF or greater ceramic capacitor and must not exceed VSYS voltage.
5 PVIN_B1_2 power_in 2nd power input for Buck1 sharing the bypass capacitor of pin 4; must not exceed VSYS voltage.
6 PVIN_LDO1 power_in Power input for LDO1; voltage must not exceed voltage on VSYS pin.
7 VLDO1 power_out Output of LDO1, nominal voltage configured in EEPROM; bypass to ground with 2.2 µF or greater ceramic capacitor.
8 GPO1 output General purpose open-drain output configurable in power-up/power-down sequence to enable an external rail.
9 SDA bidirectional I2C serial data pin; logic levels depend on the external pull-up voltage.
10 SCL input I2C serial clock pin; logic levels depend on the external pull-up voltage.
11 nINT output Open-drain interrupt request output pulled low for fault conditions and released when the bit is cleared.
12 VSEL_SD/VSEL_DDR input Multi-function pin configured as VSEL_SD (SD-card IO voltage select for LDO1 or LDO2, 1.8 V vs register VOUT) or VSEL_DDR (DDR voltage selection for Buck3).
13 VSYS power_in Input supply pin for reference system; bypass to ground with 2.2 µF or greater ceramic capacitor.
14 VDD1P8 power_out Internal reference voltage for internal use only; bypass to ground with 2.2 µF or greater ceramic capacitor.
15 AGND power_in Ground pin for analog ground.
16 GPIO bidirectional Configurable as general purpose open-drain output (GPO) or as level-sensitive synchronizing I/O for multiple TPS65220 devices.
17 GPO2 output General purpose open-drain output configurable in power-up/power-down sequence to enable an external rail.
18 nRSTOUT output Reset output to SoC controlled by sequencer; high in ACTIVE and STBY state.
19 VLDO2 power_out Output of LDO2, nominal voltage configured in EEPROM; bypass to ground with 2.2 µF or greater ceramic capacitor.
20 PVIN_LDO2 power_in Power input for LDO2; bypass with 2.2 µF or greater ceramic capacitor and must not exceed VSYS voltage.
21 VLDO3 power_out Output of LDO3, nominal voltage configured in EEPROM; bypass to ground with 2.2 µF or greater ceramic capacitor.
22 PVIN_LDO34 power_in Power input for LDO3 and LDO4; bypass with 4.7 µF or greater ceramic capacitor and must not exceed VSYS voltage.
23 VLDO4 power_out Output of LDO4, nominal voltage configured in EEPROM; bypass to ground with 2.2 µF or greater ceramic capacitor.
24 FB_B3 input Feedback input for Buck3; connect to Buck3 output filter, nominal output voltage configured in EEPROM.
25 EN/PB/VSENSE input ON-request input configurable as EN, push-button monitor (600 ms low ON-request, 8 s low OFF-request) or VSENSE power-fail comparator input.
26 PVIN_B3 power_in Power input for Buck3; bypass with 4.7 µF or greater ceramic capacitor and must not exceed VSYS voltage.
27 LX_B3 passive Switch pin for Buck3; connect one side of the Buck3 inductor to this pin.
28 MODE/RESET input Multi-function pin configured as MODE (forces PWM or permits auto PFM) or RESET (forces WARM or COLD reset); polarity configurable.
29 LX_B2 passive Switch pin for Buck2; connect one side of the Buck2 inductor to this pin.
30 PVIN_B2 power_in Power input for Buck2; bypass with 4.7 µF or greater ceramic capacitor and must not exceed VSYS voltage.
31 MODE/STBY input Level-sensitive multi-function pin configured as MODE (PWM/PFM control), STBY (low-power mode disabling selected rails) or both.
32 FB_B2 input Feedback input for Buck2; connect to Buck2 output filter, nominal output voltage configured in EEPROM.
33 PGND power_in Exposed thermal pad power ground; must be connected to a continuous ground plane with multiple vias directly underneath.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS6522053RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps6522053rhbr-etched.step / tps6522053rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps6522053rhbr.step / tps6522053rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (160 pp, sha256 e94a7b5f5d3d8c49, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF