# TPS65218D0RSLR

**Texas Instruments** · Battery Management ICs · VQFN-48-EP(6x6)

TPS65218D0RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN_DCDC1 | power_in | Input supply pin for DCDC1. |
| 2 | SDA | bidirectional | Data line for the I2C interface; connect to pullup resistor. |
| 3 | SCL | input | Clock input for the I2C interface; connect to pullup resistor. |
| 4 | LDO1 | power_out | Output voltage pin for LDO1; connect to capacitor. |
| 5 | IN_LDO1 | power_in | Input supply pin for LDO1. |
| 6 | IN_LS3 | power_in | Input supply pin for load switch 3. |
| 7 | LS3 | power_out | Output voltage pin for load switch 3; connect to capacitor. |
| 8 | PGOOD | output | Power-good output (open drain); pulled low when DCDC1-4 or LDO1 are out of regulation, and load switches and DCDC5-6 do not affect it. |
| 9 | AC_DET | input | AC monitor input and enable for DCDC1-4, LDO1 and load switches; tie to IN_BIAS if not used. |
| 10 | nPFO | output | Power-fail comparator output, deglitched (open drain); pulled low when the PFI input is below the power-fail threshold. |
| 11 | GPIO1 | bidirectional | Pin configured as DDR reset input (driving GPO2) or as a general-purpose open-drain output. |
| 12 | IN_DCDC4 | power_in | Input supply pin for DCDC4. |
| 13 | L4A | power_out | Switch pin for DCDC4; connect to inductor. |
| 14 | L4B | power_out | Switch pin for DCDC4; connect to inductor. |
| 15 | DCDC4 | power_out | Output voltage pin for DCDC4; connect to capacitor. |
| 16 | PFI | input | Power-fail comparator input; connect to resistor divider. |
| 17 | DC34_SEL | input | Power-up default selection pin for DCDC3 or DCDC4, programmed by a resistor connected to ground. |
| 18 | IN_nCC | output | Push-pull output that is pulled low when the PMIC is powered from the coin-cell battery (CC) and pulled high when powered from the main supply (IN_BU). |
| 19 | PGOOD_BU | output | Push-pull power-good output for DCDC5 and DCDC6; pulled low when either rail is out of regulation and pulled high to the DCDC6 output voltage when both are in regulation. |
| 20 | L5 | power_out | Switch pin for DCDC5; connect to inductor. |
| 21 | FB5 | input | Feedback voltage pin for DCDC5; connect to output capacitor. |
| 22 | FB6 | input | Feedback voltage pin for DCDC6; connect to output capacitor. |
| 23 | L6 | power_out | Switch pin for DCDC6; connect to inductor. |
| 24 | SYS_BU | power_out | System voltage pin for the battery-backup supply power path; connect to a 1-µF capacitor, and connecting any external load is not recommended. |
| 25 | CC | power_in | Coin-cell battery input that supplies DCDC5 and DCDC6 if no voltage is applied to IN_BU; tie to ground if not in use. |
| 26 | GPIO3 | bidirectional | Pin configurable as warm reset (negative edge) for DCDC1/2 or as a general-purpose open-drain output. |
| 27 | IN_BU | power_in | Default input supply pin for the battery backup supplies (DCDC5 and DCDC6). |
| 28 | N/C | unconnected | No connect; leave pin floating. |
| 29 | N/C | unconnected | No connect; leave pin floating. |
| 30 | LS1 | power_out | Output voltage pin for load switch 1; connect to capacitor. |
| 31 | IN_LS1 | power_in | Input supply pin for load switch 1. |
| 32 | IN_LS2 | power_in | Input supply pin for load switch 2. |
| 33 | LS2 | power_out | Output voltage pin for load switch 2; connect to capacitor. |
| 34 | GPO2 | output | DDR reset signal controlled by GPIO1 or a general-purpose output; buffer can be configured as push-pull or open-drain. |
| 35 | INT_LDO | power_out | Internal bias voltage; connect to a 1-µF capacitor, and TI does not recommend connecting any external load to this pin. |
| 36 | IN_BIAS | power_in | Input supply pin for the reference system. |
| 37 | IN_DCDC3 | power_in | Input supply pin for DCDC3. |
| 38 | L3 | power_out | Switch pin for DCDC3; connect to inductor. |
| 39 | FB3 | input | Feedback voltage pin for DCDC3; connect to output capacitor. |
| 40 | nWAKEUP | output | Signal to the SOC indicating a power-on event (active low, open-drain output). |
| 41 | FB2 | input | Feedback voltage pin for DCDC2; connect to output capacitor. |
| 42 | L2 | power_out | Switch pin for DCDC2; connect to inductor. |
| 43 | IN_DCDC2 | power_in | Input supply pin for DCDC2. |
| 44 | PB | input | Push-button monitor input, typically connected to a momentary switch to ground (active low). |
| 45 | nINT | output | Interrupt output (active low, open drain) that is pulled low when an interrupt bit is set and returns to Hi-Z after the causing bit is read; interrupts can be masked. |
| 46 | PWR_EN | input | Power enable input for DCDC1-4, LDO1 and load switches. |
| 47 | FB1 | input | Feedback voltage pin for DCDC1; connect to output capacitor. |
| 48 | L1 | power_out | Switch pin for DCDC1; connect to inductor. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(6x6) |
| Category | Power Supply Chip |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage IN_BIAS, IN_LDO1, IN_LS2, IN_DCDC1, IN_DCDC2, IN_DCDC3, IN_DCDC4 |  | -0.3 |  | 7 | V |  | 7 |
| Supply voltage IN_LS1, CC |  | -0.3 |  | 3.6 | V |  | 7 |
| Supply voltage IN_LS3 |  | -0.3 |  | 11.2 | V |  | 7 |
| Supply voltage IN_BU |  | -0.3 |  | 5.8 | V |  | 7 |
| Input voltage (all pins) |  | -0.3 |  | 7 | V | All pins unless specified separately | 7 |
| Output voltage (all pins) |  | -0.3 |  | 7 | V | All pins unless specified separately | 7 |
| Source current GPO2 |  |  |  | 6 | mA |  | 7 |
| Source current PGOOD_BU, IN_nCC |  |  |  | 1 | mA |  | 7 |
| Sink current PGOOD, nWAKEUP, nINT, nPFO, SDA, GPIO1, GPIO3 |  |  |  | 6 | mA |  | 7 |
| Operating ambient temperature | TA | -40 |  | 105 | °C |  | 7 |
| Junction temperature | TJ | -40 |  | 125 | °C |  | 7 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 7 |
| Electrostatic discharge, Human-body model (HBM) | V(ESD) | -2000 |  | 2000 | V | Per ANSI/ESDA/JEDEC JS-001 | 7 |
| Electrostatic discharge, Charged-device model (CDM) | V(ESD) | -500 |  | 500 | V | Per JEDEC JESD22-C101 | 7 |
| Supply voltage, IN_BIAS |  | 2.7 |  | 5.5 | V |  | 8 |
| Input voltage for DCDC1, DCDC2, DCDC3, DCDC4 |  | 2.7 |  | 5.5 | V |  | 8 |
| Supply voltage, IN_BU |  | 2.2 |  | 5.5 | V |  | 8 |
| Supply voltage, CC |  | 2.2 |  | 3.3 | V |  | 8 |
| Input voltage for LDO1 |  | 1.8 |  | 5.5 | V |  | 8 |
| Input voltage for LS1 |  | 1.2 |  | 3.6 | V |  | 8 |
| Input voltage for LS2 |  | 3 |  | 5.5 | V |  | 8 |
| Input voltage for LS3 |  | 1.8 |  | 10 | V |  | 8 |
| Output voltage for DCDC1 |  | 0.85 |  | 1.675 | V |  | 8 |
| Output voltage for DCDC2 |  | 0.85 |  | 1.675 | V |  | 8 |
| Output voltage for DCDC3 |  | 0.9 |  | 3.4 | V |  | 8 |
| Output voltage for DCDC4 |  | 1.175 |  | 3.4 | V |  | 8 |
| Output voltage for LDO1 |  | 0.9 |  | 3.4 | V |  | 8 |
| Output current for DCDC1, DCDC2, DCDC3 |  | 0 |  | 1.8 | A |  | 8 |
| Output current for DCDC4 |  |  |  | 1 | A | VIN_DCDC4 = 2.8 V | 8 |
| Output current for DCDC4 |  |  |  | 1.3 | A | VIN_DCDC4 = 3.6 V | 8 |
| Output current for DCDC4 |  |  |  | 1.6 | A | VIN_DCDC4 = 5 V | 8 |
| Output current for DCDC5, DCDC6 |  | 0 |  | 25 | mA |  | 8 |
| Output current for LDO1 |  | 0 |  | 400 | mA |  | 8 |
| Output current for LS1 |  | 0 |  | 300 | mA |  | 8 |
| Output current for LS2 |  | 0 |  | 920 | mA |  | 8 |
| Output current for LS3 |  | 0 |  | 900 | mA | VIN_LS3 > 2.3 V | 8 |
| Output current for LS3 |  | 0 |  | 475 | mA | VIN_LS3 ≤ 2.3 V | 8 |
| Supply voltage range, EEPROM programming (VIN_BIAS) | VIN_BIAS | 4.5 |  | 5.5 | V | EEPROM programming | 9 |
| SYS_BU voltage range | VSYS_BU | 2.2 |  | 5.5 | V | Powered from VIN_BU or VCC | 9 |
| Tolerance, SYS_BU recommended capacitor (CSYS_BU) |  | -20 |  | 20 | % | Ceramic, X5R or X7R, rated voltage ≥ 6.3 V | 9 |
| INT_LDO DC accuracy | VINT_LDO | -2 |  | 2 | % | IOUT < 10 mA | 9 |
| DCDC1 DC accuracy | VDCDC1 | -2 |  | 2 | % | 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A | 9 |
| DCDC1 dynamic accuracy, in respect to nominal output voltage |  | -2.5 |  | 2.5 | % | IOUT = 50 mA to 450 mA in < 1 µs; COUT ≥ 10 µF | 9 |
| DCDC1 quiescent current | IQ |  | 25 | 50 | µA | Total current from IN_DCDC1 pin; device not switching, no load | 9 |
| DCDC1 high-side FET on resistance | RDS(ON) |  | 230 | 355 | mΩ | VIN_DCDC1 = 3.6 V | 9 |
| DCDC1 power-good threshold (VOUT falling) | VPG | 88.5 | 90 | 91.5 | % | STRICT = 0b | 10 |
| DCDC1 nominal inductor value | L | 1 | 1.5 | 2.2 | µH | See Table 6-2 | 10 |
| DCDC1 inductor tolerance | L | -30 |  | 30 | % |  | 10 |
| LS1 static on resistance | RDS(ON) |  |  | 110 | mΩ | VIN_LS1 = 3.3 V, IOUT = 300 mA, over full temperature range | 15 |
| LS2 static on resistance | RDS(ON) |  |  | 500 | mΩ | VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature range | 16 |
| LDO1 DC accuracy | VOUT | -2 |  | 2 | % | VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA | 15 |
| Overtemperature shutdown TOTS | TOTS | 135 | 145 | 155 | °C | Increasing junction temperature | 18 |
| Oscillator frequency accuracy | ƒOSC | -12 |  | 12 | % | TJ = -40°C to +105°C | 18 |
| Thermal resistance, junction-to-case (top), RSL (VQFN) | RθJC(top) |  | 17.2 |  | °C/W |  | 8 |
| Thermal resistance, junction-to-board, RSL (VQFN) | RθJB |  | 5.8 |  | °C/W |  | 8 |
| Thermal resistance, junction-to-ambient, RSL (VQFN) | RθJA |  | 30.6 |  | °C/W | JEDEC 4-layer, high-K board | 8 |
| Junction-to-package top, RSL (VQFN) | ΨJT |  | 0.2 |  | °C/W |  | 8 |
| Junction-to-board, RSL (VQFN) | ΨJB |  | 5.6 |  | °C/W |  | 8 |
| Thermal resistance, junction-to-case (bottom), RSL (VQFN) | RθJC(bot) |  | 1.5 |  | °C/W |  | 8 |

## CAD (KiCad official)

- Symbol: `TPS65218D0RSLR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm`
- 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps65218d0rslr-etched.step` / `tps65218d0rslr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps65218d0rslr.step` / `tps65218d0rslr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65218d0) (114 pp, sha256 `964ee3a324d5772d`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps65218d0rslr-datasheet.pdf)