component
TPS65185RSLR
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Texas Instruments Power Management - Specialized, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65185RSLR
Texas Instruments · Power Management - Specialized · VQFN-48-EP(6x6)
TPS65185RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Filter pin for 2.25-V internal reference to ADC. Connect a 4.7-µF capacitor from this pin to ground. |
| 2 | INT | output | Open drain interrupt pin (active low). |
| 3 | VNEG | output | Negative supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground. |
| 4 | VNEG_IN | power_in | Input pin for LDO2 (VNEG). Connect a 4.7-µF capacitor from this pin to ground. |
| 5 | WAKEUP | input | Wake up pin (active high). Pull this pin high to wake up from sleep mode. |
| 6 | DGND | power_in | Digital ground. Connect to ground plane. |
| 7 | INT_LDO | output | Filter pin for 2.7-V internal supply. Connect a 4.7-µF capacitor from this pin to ground. |
| 8 | AGND1 | power_in | Analog ground for general analog circuitry. |
| 9 | VNEG_DIS | output | Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the rail is disabled. |
| 10 | VIN | power_in | Input power supply to general circuitry. Connect a 10-µF capacitor from this pin to ground. |
| 11 | N/C | unconnected | Not internally connected. |
| 12 | VCOM_CTRL | input | VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low and VN is enabled, VCOM discharge is enabled. |
| 13 | N/C | unconnected | Not internally connected. |
| 14 | VCOM_DIS | input | Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever VCOM is disabled. |
| 15 | VCOM | output | Filter pin for panel common-voltage driver. Connect a 4.7-µF capacitor from this pin to ground. |
| 16 | VCOM_PWR | power_in | Internal supply input pin to VCOM buffer. Connect to the output of DCDC2, and connect a 4.7-µF capacitor from this pin to ground. |
| 17 | SCL | input | Serial interface (I2C) clock input. |
| 18 | SDA | bidirectional | Serial interface (I2C) data input/output. |
| 19 | VPOS_DIS | input | Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge VPOS to ground whenever the rail is disabled. |
| 20 | N/C | unconnected | Not internally connected. |
| 21 | PWRUP | input | Power-up pin. Pull this pin high to power up all output rails. |
| 22 | PBKG | passive | Die substrate. Connect to the VN pin (-16 V) with a short, wide trace. A wide copper trace improves heat dissipation. |
| 23 | PWR_GOOD | output | Open-drain power good output pin. Pin is pulled low when one or more rails are disabled or not in regulation. |
| 24 | VIN_P | power_in | Input power supply to inverting buck-boost converter (DCDC2). Connect a 10-µF capacitor from this pin to ground. |
| 25 | VN_SW | output | Inverting buck-boost converter switch out (DCDC2). |
| 26 | VN | power_in | Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and VEE charge pump. Connect a 4.7-µF capacitor from this pin to ground. |
| 27 | VEE_IN | power_in | Input supply pin for negative charge pump (CP2) (VEE). |
| 28 | VEE_DRV | output | Driver output pin for negative charge pump (CP2). |
| 29 | VEE_DIS | input | Discharge pin for VEE. Connect a resistor from VEE_DIS to VEE to discharge VEE to ground whenever the rail is disabled. |
| 30 | VEE_D | output | Base voltage output pin for negative charge pump (CP2). Connect a 100-nF capacitor from this pin to ground. |
| 31 | VEE_FB | input | Feedback pin for negative charge pump (CP2). |
| 32 | PGND2 | power_in | Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps. |
| 33 | VDDH_FB | input | Feedback pin for positive charge pump (CP1). |
| 34 | VDDH_D | output | Base voltage output pin for positive charge pump (CP1). Connect a 100-nF capacitor from this pin to ground. |
| 35 | VDDH_DIS | input | Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the rail is disabled. |
| 36 | VDDH_DRV | output | Driver output pin for positive charge pump (CP1). |
| 37 | VDDH_IN | power_in | Input supply pin for positive charge pump (CP1). |
| 38 | N/C | unconnected | Not internally connected. |
| 39 | N/C | unconnected | Not internally connected. |
| 40 | VB_SW | output | Boost converter switch out (DCDC1). |
| 41 | PGND1 | power_in | Power ground for DCDC1. |
| 42 | VB | power_in | Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge pump. Connect a 4.7-µF capacitor from this pin to ground. |
| 43 | VPOS_IN | power_in | Input pin for LDO1 (VPOS). Connect a 4.7-µF capacitor from this pin to ground. |
| 44 | VPOS | output | Positive supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground. |
| 45 | VIN3P3 | power_in | Input pin to 3.3-V power switch. |
| 46 | V3P3 | output | Output pin of 3.3-V power switch. |
| 47 | TS | input | Thermistor input pin. Connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND. |
| 48 | AGND2 | power_in | Reference point to external thermistor and linearization resistor. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TPS65185RSLR - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm - 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps65185rslr-etched.step/tps65185rslr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65185rslr.step/tps65185rslr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
903effae4b79ef29, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).