Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS65161APWPR

Texas Instruments · Power Management - Specialized · HTSSOP-28-EP

TPS65161APWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FB	input	Feedback of the main boost converter generating Vsource (VS).
2	COMP	output	Compensation pin for the main boost converter; connect a capacitor and, if required, a resistor to this pin for frequency compensation.
3	OS	input	Output sense pin for the boost converter overvoltage protection; must be connected to boost converter output with a 470-nF capacitor to GND; use wide PCB trace due to high current.
4	SW	output	Switch pin of the boost converter generating Vsource (VS).
5	SW	output	Switch pin of the boost converter generating Vsource (VS).
6	PGND	power_in	Power ground.
7	PGND	power_in	Power ground.
8	SUP	power_in	Supply pin of the positive charge pump driver; can be connected to VIN or the main boost converter output VS depending on the desired output voltage VGH.
9	EN2	input	Enable pin of the boost converter and positive charge pump; logic high enables the device after the buck converter is within regulation and delay time DLY2.
10	DRP	output	Drive pin of the positive charge pump.
11	DRN	output	Drive pin of the negative charge pump.
12	FREQ	input	Frequency adjust pin; logic low sets 500 kHz switching frequency and logic high sets 750 kHz switching frequency.
13	FBN	input	Feedback pin of negative charge pump.
14	FBP	input	Feedback pin of positive charge pump.
15	FBB	input	Feedback pin of the buck converter.
16	EN1	input	Enable pin of the buck converter and negative charge pump; logic high enables the device and after delay time DLY1, the negative charge pump starts.
17	BOOT	output	N-channel MOSFET gate drive voltage for the buck converter; connect a capacitor from the switch node SWB to this pin.
18	SWB	output	Switch pin of the buck converter.
19	NC	unconnected	Not connected.
20	VINB	power_in	Power input voltage pin for the buck converter.
21	VINB	power_in	Power input voltage pin for the buck converter.
22	AVIN	power_in	Analog input voltage for the analog circuits; bypass with a 1-μF ceramic capacitor for filtering.
23	GND	power_in	Analog ground.
24	REF	output	Internal reference voltage output of 1.213 V typical; connect a 220-nF capacitor to this pin.
25	DLY1	output	Delay timing pin; connecting a capacitor from this pin to GND sets the delay time between V(LOGIC) and VGL during start-up.
26	DLY2	output	Delay timing pin; connecting a capacitor from this pin to GND sets the delay time between V(LOGIC) and VS/VGH during start-up.
27	GD	tri_state	Gate drive pin for external MOSFET isolation switch; open-drain output latched low when boost converter is within 8% of regulation; goes high impedance when EN2 is cycled low.
28	SS	output	Soft-start timing pin; connect a 22-nF capacitor to this pin to set the soft-start time for the boost converter.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Power Management (PMIC)
Pins	29

CAD (KiCad official)

Symbol: TPS65161APWPR
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: tps65161apwpr-etched.step / tps65161apwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65161apwpr.step / tps65161apwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (36 pp, sha256 a7de02a273004393, retrieved 2026-10-06, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF