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TPS65149RSHR

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Texas Instruments Power Management Specialized - PMIC, VQFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS65149RSHR

Texas Instruments · Power Management Specialized - PMIC · VQFN-56-EP(7x7)

TPS65149RSHR from Texas Instruments, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FBPH input A resistor to ground sets the positive charge pump's maximum (cold) output voltage, with 200 µA flowing out of the pin to give the feedback voltage.
2 COMP input Boost converter compensation pin; connect a compensation network (a series RC is adequate for most applications) to ground.
3 AGND power_in Analog ground.
4 SS input A capacitor to ground sets the boost converter soft-start; larger values lengthen start-up time and reduce inrush current from VIN.
5 RHVS output A resistor between this pin and FB sets the boost converter output voltage in high voltage stress mode.
6 FB input Boost converter feedback pin.
7 PGND power_in Power ground.
8 PGND power_in Power ground.
9 SW passive Boost converter switch node.
10 SW passive Boost converter switch node.
11 FREQ input Boost switching frequency select: 1.2 MHz when high, 640 kHz when low; internal pull-up, may be left floating for 1.2 MHz.
12 GD output Gate drive for the external isolation switch; sinks a constant current when EN=high and is pulled up by a resistor when EN=low.
13 VIN power_in Supply voltage input (3 V to 6 V); decouple with a 100 nF ceramic capacitor close to the pin.
14 XAO output Open-drain reset output pulled low when the VDET voltage is below the internal 1.24 V reference.
15 EN input Enable input: device enabled when high and disabled when low; the panel discharge function always works regardless of EN.
16 VDET input Panel discharge detection; discharge mode is entered when the voltage is below the internal reference (1.24 V), which also pulls XAO low.
17 HVS input High voltage stress mode when high, normal mode when low; internal pull-down, may be left floating in normal operation.
18 AVDD power_in Must connect to the boost converter output; used as the VCOM reference and for boost overvoltage and short-circuit detection.
19 DVRO input Current sink programmable via I2C, typically connected to a resistor divider between AVDD and ground to set the external VCOM buffer input voltage.
20 RSET input A resistor to ground sets the full-scale current of the DVRO current sink; smaller values give larger currents.
21 WP input EEPROM write protect: data can be overwritten only when WP=high; all EEPROM writes are prevented when low.
22 SCL bidirectional I2C interface clock signal.
23 SDA bidirectional I2C interface data signal.
24 NC unconnected Not connected; leave floating or connect to ground.
25 LGND power_in Level shifter ground connection.
26 DSCHG2 output Level shifter output (panel discharge signal 2).
27 CLKOUT1 output Level shifter output.
28 CLKOUT2 output Level shifter output.
29 CLKOUT3 output Level shifter output.
30 CLKOUT4 output Level shifter output.
31 CLKOUT5 output Level shifter output.
32 CLKOUT6 output Level shifter output.
33 STVOUT output Level shifter output.
34 RESETOUT output Level shifter output.
35 DSCHG1 output Level shifter output (panel discharge signal 1).
36 RESETIN input Level shifter input.
37 STVIN input Level shifter input.
38 CLKIN6 input Level shifter input.
39 CLKIN5 input Level shifter input.
40 CLKIN4 input Level shifter input.
41 CLKIN3 input Level shifter input.
42 CLKIN2 input Level shifter input.
43 CLKIN1 input Level shifter input.
44 VGH power_in Level shifter positive supply; decouple with a 0.1 µF to 10 µF ceramic capacitor close to the pin.
45 NC unconnected Not connected; leave floating or connect to ground.
46 VGL1 power_in Level shifter negative supply for all channels except DSCHRG2; decouple with a 0.1 µF to 10 µF ceramic capacitor close to the pin.
47 VGL2 power_in Level shifter negative supply for the DSCHRG2 channel; decouple with a 0.1 µF to 10 µF ceramic capacitor close to the pin.
48 NC unconnected Not connected; leave floating or connect to ground.
49 FBN input Negative charge pump controller feedback pin.
50 VL output Accurate reference voltage for the negative charge pump, not for external loads; decouple with a 0.1 µF to 1 µF ceramic capacitor close to the pin.
51 DRVN output Base drive current for the external NPN transistor regulating VGL1.
52 FBP input Positive charge pump controller feedback pin.
53 NC unconnected Not connected; leave floating or connect to ground.
54 DRVP output Base drive current for the external PNP transistor regulating VGH.
55 NC unconnected Not connected; leave floating or connect to ground.
56 RNTC input A thermistor-resistor network on this pin programs the temperature compensation characteristic of the positive charge pump.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-56-EP(7x7)
Category Power Supply Chip
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 3 5 6 V 3
Boost converter output voltage range VAVDD 7 18 V Or VIN + 1 V, whichever is lower 3
Level shifter positive supply voltage range VGH 15 38 V 3
Level shifter negative supply voltage range VGL1 -3 -15 V 3
Programmable VCOM set current ISET 0.1 0.5 mA 3
VL decoupling capacitance CL 10 100 220 nF 3
Operating ambient temperature TA -40 25 85 °C 3
Operating junction temperature TJ -40 85 125 °C 3
Pin voltage (control/logic pins) 7 V FBN, VL, WP, SCL, SDA, FBP, RESETIN, CLKIN1-6, FBPH, FREQ, COMP, RHVS, FB, SS, GD, VIN, DRVN, VDET, STVIN, RNTC, RSET, EN, XAO; wrt AGND and LGND 2
Pin voltage (DVRO, AVDD, SW, HVS) 20 V wrt AGND and LGND 2
Pin voltage (DRVP, VGH) 40 V wrt AGND and LGND 2
Pin voltage (VGL1, VGL2) -20 V wrt AGND and LGND 2
Pin voltage (DSCHG1, DSCHRG2, STVOUT, RESETOUT, CLKOUT1-6) -20 40 V wrt AGND and LGND 2
ESD Human Body Model 2 kV 2
ESD Machine Model 200 V 2
ESD Charged Device Model 500 V 2
Ambient temperature TA -40 85 °C 2
Junction temperature TJ -40 150 °C 2
Storage temperature TSTG -65 150 °C 2
Lead temperature 300 °C soldering, 10 seconds 2
Reference voltage VL 1.215 1.24 1.265 V IL = 100 µA 3
Feedback regulation voltage (boost) VFB 1.228 1.24 1.252 V 4
Feedback input bias current IFB -100 100 nA VFB = 1.24V 4
Switch ON resistance rDS(ON) 0.13 0.18 Ω VIN = 5V, ISW = ILIM 4
Switch current limit ILIM 4 4.6 5.6 A 4
Overvoltage threshold VOVP 18 19 20 V VAVDD rising 4
Oscillator frequency fSW 900 1200 1500 kHz FREQ connected to VIN 4
Oscillator frequency fSW 470 640 790 kHz FREQ connected to 0V 4
HVS switch ON resistance RHVS 400 500 600 Ω HVS = 5 V, RHVS = 0 V 4
Positive charge pump feedback regulation voltage VFBP 1.663 1.75 1.838 V Lower limit; VRNTC = 2 V, VFBPH = 1.75 V 4
Positive charge pump feedback regulation voltage VFBP 1.425 1.5 1.575 V Lower limit; VRNTC = 1.5 V, VFBPH = 1.75 V 4
Positive charge pump feedback regulation voltage VFBP 1.178 1.24 1.302 V Lower limit; VRNTC = 1.0 V, VFBPH = 1.75 V 4
FBP input bias current IFBP -100 100 nA VRNTC = 1 V, VFBPH = 1.75 V, VFBP = 1.24 V 4
RNTC output current IRNTC 190 200 210 µA VRNTC = 1.5 V, matched to IFBPH; TA = 25 °C 4
FBPH output current IFBPH 195 200 205 µA VFBPH = 1.75 V, trimmed; at TA = 25 °C 4
Short circuit sink current DRVP IDRVP 40 72 µA Short-circuit operation, sinking, VFBP = 0 V, VDRVP = 28 V 4
FBN feedback regulation voltage VFBN -15 15 mV IDRVN = 1 mA, sourcing 5
FBN input bias current IFBN -100 100 nA VFBN = 0 V 5
DRVN short-circuit source current IDRVN 200 300 480 µA Short-circuit operation, sourcing, VFBN = 1.116 V, VDRVN = 0.7 V 5
Level shifter UVLO threshold VUVLO 5 7.5 10 V VGH rising 5
Discharge threshold voltage VIL(DET) 1.221 1.24 1.259 V VDET falling 5
Junction-to-ambient thermal resistance θJA 27.4 °C/W QFN 56 pins 2
Junction-to-case(top) thermal resistance θJC(top) 20.4 °C/W 2
Junction-to-board thermal resistance θJB 7.1 °C/W 2
Junction-to-case(bottom) thermal resistance θJC(bottom) 2.2 °C/W 2
VIN supply current IIN 0.75 mA Device not switching, VFB = VL+5% 3
UVLO threshold VUVLO 2.5 V VIN rising 3
Thermal shutdown threshold TSD 138 °C 5

CAD (KiCad official)

  • Symbol: TPS65149RSHR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: tps65149rshr-etched.step / tps65149rshr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65149rshr.step / tps65149rshr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 e7765480c38b6fc4, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF