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TPS65141RGER
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTPS65141RGER
Texas Instruments · Power Management - Specialized · VQFN-24-EP(4x4)
TPS65141RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Compensation pin for the main boost converter; a small capacitor is connected to this pin. |
| 2 | ENR | input | Enable pin of the linear regulator controller; it must be terminated and not left floating, a logic high enables the regulator and a logic low puts it in shutdown. |
| 3 | EN | input | Enable pin of the device; it must be terminated and not left floating, a logic high enables the device and a logic low shuts it down. |
| 4 | FB1 | input | Feedback pin of the boost converter. |
| 5 | FB4 | input | Feedback pin of the linear regulator controller, which is set to a fixed output voltage of 3.3 V or 3 V depending on the version. |
| 6 | BASE | output | Base drive output for the external transistor. |
| 7 | VIN | power_in | Input voltage pin of the device; recommended input voltage range is 2.7 V to 5.8 V and the absolute maximum voltage on VIN is 6 V. |
| 8 | SW | input | Switch pin of the boost converter; absolute maximum voltage on SW is 20 V. |
| 9 | SW | input | Switch pin of the boost converter; absolute maximum voltage on SW is 20 V. |
| 10 | PGND | power_in | Power ground; the PowerPAD or exposed thermal die must be connected to the power ground pins. |
| 11 | PGND | power_in | Power ground; the PowerPAD or exposed thermal die must be connected to the power ground pins. |
| 12 | SUP | power_in | Supply pin of the positive and negative charge pumps, boost converter and gate drive circuit; it must be connected to the output of the main boost converter and cannot be connected to any other voltage source. |
| 13 | PG | output | Open-drain output indicating when all outputs VO1, VO2 and VO3 are within 10% of their nominal output voltage; it goes low when one of the outputs falls below 10% of its nominal output voltage. |
| 14 | GND | power_in | Ground. |
| 15 | FB3 | input | Feedback pin of the positive charge pump. |
| 16 | OUT3 | power_out | Positive charge pump output. |
| 17 | C2+ | passive | Positive terminal for the charge pump flying capacitor; if the device runs in voltage doubler mode, this pin must be left open. |
| 18 | C2-/MODE | passive | Negative terminal of the charge pump flying capacitor and charge pump MODE pin; a flying capacitor connected here gives voltage tripler mode, while for voltage doubler mode the capacitor is removed and this pin must be connected to GND. |
| 19 | C1+ | passive | Positive terminal of the charge pump flying capacitor. |
| 20 | C1- | passive | Negative terminal of the charge pump flying capacitor. |
| 21 | DRV | output | External charge pump driver output. |
| 22 | GND | power_in | Ground. |
| 23 | REF | output | Internal reference output, typically 1.23 V. |
| 24 | FB2 | input | Feedback pin of the negative charge pump. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltages on pin VIN | -0.3 | 6 | V | 4 | |||
| Voltages on pin VO1, SUP, PG | -0.3 | 15.5 | V | 4 | |||
| Voltages on pin EN, MODE, ENR | -0.3 | V | max printed as VI + 0.3 V | 4 | |||
| Voltage on pin SW | 20 | V | 4 | ||||
| Power good maximum sink current (PG) | 1 | mA | 4 | ||||
| Lead temperature (soldering) | 260 | °C | soldering, 10 s | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD human-body model (HBM) | V(ESD) | -2000 | 2000 | V | Human-body model, per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD charged-device model (CDM) | V(ESD) | -500 | 500 | V | Charged-device model, per JEDEC JESD22-C101 | 4 | |
| Input voltage (recommended) | VI | 2.7 | 5.8 | V | 4 | ||
| Operating ambient temperature | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 4 | ||
| Input voltage | VI | 2.7 | 5.5 | V | 5 | ||
| Quiescent current into VIN | IQ | 0.7 | 0.9 | mA | ENR = GND, VO3 = 2 × VO1, boost converter not switching | 5 | |
| Charge pump quiescent current into SUP | IQCharge | 1.7 | 2.7 | mA | VO1 = SUP = 10 V, VO3 = 2 × VO1 | 5 | |
| Charge pump quiescent current into SUP | IQCharge | 3.9 | 6 | mA | VO1 = SUP = 10 V, VO3 = 3 × VO1 | 5 | |
| LDO controller quiescent current into VIN | IQEN | 300 | 800 | µA | ENR = VIN, EN = GND | 5 | |
| Shutdown current into VIN | ISD | 1 | 10 | µA | EN = ENR = GND | 5 | |
| Undervoltage lockout threshold | VUVLO | 2.2 | 2.4 | V | VI falling | 5 | |
| High level input voltage (EN, ENR) | VIH | 1.5 | V | 5 | |||
| Low level input voltage (EN, ENR) | VIL | 0.4 | V | 5 | |||
| Output voltage VO1 | VO1 | 5 | 15 | V | 5 | ||
| Minimum input to output voltage difference | VO1, VIN | 1 | V | 5 | |||
| Reference voltage | VREF | 1.205 | 1.213 | 1.219 | V | 5 | |
| Feedback regulation voltage | VFB | 1.136 | 1.146 | 1.154 | V | 5 | |
| Feedback input bias current | IFB | 10 | 100 | nA | 5 | ||
| N-MOSFET ON-resistance (Q1) | rDS(on) | 195 | 290 | mΩ | VO1 = 10 V, ISW = 500 mA | 5 | |
| N-MOSFET ON-resistance (Q1) | rDS(on) | 285 | 420 | mΩ | VO1 = 5 V, ISW = 500 mA | 5 | |
| N-MOSFET switch current limit (Q1) | ILIM | 1.6 | 2.3 | 2.6 | A | TPS65140, TPS65141 | 5 |
| P-MOSFET ON-resistance (Q2) | rDS(on) | 9 | 15 | Ω | VO1 = 10 V, ISW = 100 mA | 5 | |
| P-MOSFET ON-resistance (Q2) | rDS(on) | 14 | 22 | Ω | VO1 = 5 V, ISW = 100 mA | 5 | |
| Maximum P-MOSFET peak switch current | IMAX | 1 | A | 5 | |||
| Oscillator frequency | fSW | 1.295 | 1.6 | 2.1 | MHz | 0°C ≤ TA ≤ 85°C | 5 |
| Oscillator frequency | fSW | 1.191 | 1.6 | 2.1 | MHz | -40°C ≤ TA ≤ 85°C | 5 |
| Feedback regulation voltage (negative charge pump) | VFB | -36 | 0 | 36 | mV | VO2 negative charge pump | 6 |
| Feedback input bias current (negative charge pump) | IFB | 10 | 100 | nA | 6 | ||
| Q8 P-channel switch rDS(on) | rDS(on) | 4.3 | 8 | Ω | IO = 20 mA | 6 | |
| Q9 N-channel switch rDS(on) | rDS(on) | 2.9 | 4.4 | Ω | 6 | ||
| Maximum output current (negative charge pump) | IO | 20 | mA | 6 | |||
| Feedback regulation voltage (positive charge pump) | VFB | 1.187 | 1.214 | 1.238 | V | 6 | |
| Feedback input bias current (positive charge pump) | IFB | 10 | 100 | nA | 6 | ||
| Q3 P-channel switch rDS(on) | rDS(on) | 9.9 | 15.5 | Ω | IO = 20 mA | 6 | |
| Q4 N-channel switch rDS(on) | rDS(on) | 1.1 | 1.8 | Ω | 6 | ||
| Q5 P-channel switch rDS(on) | rDS(on) | 4.6 | 8.5 | Ω | 6 | ||
| Q6 N-channel switch rDS(on) | rDS(on) | 1.2 | 2.2 | Ω | 6 | ||
| D1, D4 Schottky diode forward voltage | VD | 610 | 720 | mV | ID1, D4 = 40 mA | 6 | |
| Maximum output current (positive charge pump) | IO | 20 | mA | 6 | |||
| Linear regulator output voltage VO4 | VO4 | 3.2 | 3.3 | 3.4 | V | 4.5 V ≤ VI ≤ 5.5 V; 10 mA ≤ IO ≤ 500 mA | 6 |
| Maximum base drive current | IBASE | 13.5 | 19 | mA | VIN, VO4, VBE ≥ 0.5 V | 6 | |
| Maximum base drive current | IBASE | 20 | 27 | mA | VIN, VO4, VBE ≥ 0.75 V | 6 | |
| Start-up current | 11 | 20 | 25 | mA | VO4 ≤ 0.8 V | 6 | |
| Power good threshold V(PG,VO1) | V(PG,VO1) | -12 | -6 | V | 7 | ||
| Power good threshold V(PG,VO2) | V(PG,VO2) | -13 | -5 | V | 7 | ||
| Power good threshold V(PG,VO3) | V(PG,VO3) | -11 | -5 | V | 7 | ||
| PG output low voltage | VOL | 0.3 | V | I(sink) = 500 μA | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 34.2 | °C/W | RGE (VQFN) 24-pin package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 11.7 | °C/W | RGE (VQFN) 24-pin package | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 35.5 | °C/W | RGE (VQFN) 24-pin package | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.2 | °C/W | RGE (VQFN) 24-pin package | 5 |
CAD (KiCad official)
- Symbol:
TPS65141RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps65141rger-etched.step/tps65141rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65141rger.step/tps65141rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
4f6d9fa944aa619e, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).