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TPS650945A0RSKR

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Texas Instruments Power Management - Specialized, VQFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps650945a0rskrfactory-2.0.0extractor-text

Verified TPS650945A0RSKR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS650945A0RSKR · VQFN-64-EP(8x8) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 92-page datasheet
  • ✓distributor: lcsc C1850383, digikey 296-TPS650945A0RSKRTR-ND, mouser 595-TPS650945A0RSKR
  • ✓family: QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-soh93yz1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps650945a0rskr.kicad_sym✓ tps650945a0rskr.kicad_mod✓ tps650945a0rskr.step
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Ray Publish 0.1.0 3cec1d1 1d ago

TPS650945A0RSKR

Texas Instruments · Power Management - Specialized · VQFN-64-EP(8x8)

TPS650945A0RSKR from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FBGND2 power_in Remote negative feedback sense for BUCK2 controller, connected to the VCCGI VSS SENSE from the SoC.
2 FBVOUT2 input Remote positive feedback sense for BUCK2 controller, connected to the VCCGI VCC SENSE from the SoC.
3 DRVH2 output High-side gate driver output for BUCK2 controller, powered from VSYS + 5 V.
4 SW2 input Switch node connection for BUCK2 controller.
5 BOOT2 input Bootstrap pin for BUCK2 controller; connect a 100-nF ceramic capacitor between this pin and SW2.
6 PGNDSNS2 power_in Power GND connection for BUCK2; connect to the ground terminal of the external low-side FET.
7 DRVL2 output Low-side gate driver output for BUCK2 controller, 5 V supply.
8 DRV5V_2_A1 input 5-V supply to BUCK2 gate driver and LDOA1; bypass with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0.
9 LDOA1 power_out LDOA1 output, 1.35-3.3 V; bypass with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
10 LX3 output Switch node connection for BUCK3 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
11 PVIN3 power_in Power input to BUCK3 converter at 5 V; bypass to ground with a 10-µF (typical) ceramic capacitor.
12 FB3 input Remote feedback sense for BUCK3 converter; connect to positive terminal of output capacitor.
13 PMICEN input PMIC cold-boot pin; a rising edge at assertion moves the power state from G3 to S4/S5, and driving it low shuts down all VRs.
14 LDOLS_EN or SWA1_EN input Enable pin for LDOA2, LDOA3 and SWA1 (LDOLS_EN) or for SWA1 only (SWA1_EN); rails turn on at assertion (H) and off at deassertion (L).
15 IRQB output Open-drain output interrupt pin; see Section 7.6.4 for register definitions.
16 RSMRSTB output Open-drain Always-ON-rail Power Good; reflects a valid state whenever VSYS is available.
17 SWB1 power_out Output of load switch B1, 0.5-3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor and short with SWB2.
18 PVINSWB1_B2 power_in Power supply to load switches B1 and B2, 0.5-3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use.
19 SWB2 power_out Output of load switch B2, 0.5-3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor and short with SWB1.
20 LX5 output Switch node connection for BUCK5 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
21 PVIN5 power_in Power input to BUCK5 converter at 5 V; bypass to ground with a 10-µF (typical) ceramic capacitor.
22 FB5 input Remote feedback sense for BUCK5 converter; connect to positive terminal of output capacitor.
23 FB4 input Remote feedback sense for BUCK4 converter; connect to positive terminal of output capacitor.
24 PVIN4 power_in Power input to BUCK4 converter at 5 V; bypass to ground with a 10-µF (typical) ceramic capacitor.
25 LX4 output Switch node connection for BUCK4 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
26 GPO output Open-drain output controlled by an I2C register bit, usable as an enable signal to an external VR.
27 PCH_PWROK output Open-drain global Power Good; reflects a valid state whenever VSYS is available.
28 PROCHOT output Optional open-drain output indicating a PMIC thermal event when any die temperature sensor detects the THOT temperature; invert before connecting to SoC if used.
29 FBVOUT1 input Remote feedback sense for BUCK1 controller, connected to the VNN VCC SENSE from the SoC.
30 ILIM1 input Current limit set pin for BUCK1 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
31 SWA1 power_out Output of load switch A1, 0.5-3.3 V; bypass with a 0.1-µF (typical) ceramic capacitor and leave floating when not in use.
32 PVINSWA1 power_in Power supply to load switch A1, 0.5-3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use.
33 DRVH1 output High-side gate driver output for BUCK1 controller, powered from VSYS + 5 V.
34 SW1 input Switch node connection for BUCK1 controller.
35 BOOT1 input Bootstrap pin for BUCK1 controller; connect a 100-nF ceramic capacitor between this pin and SW1.
36 PGNDSNS1 power_in Power GND connection for BUCK1; connect to the ground terminal of the external low-side FET.
37 DRVL1 output Low-side gate driver output for BUCK1 controller, 5 V supply.
38 DRV5V_1_6 input 5-V supply to BUCK1 and BUCK6 gate drivers; bypass with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0.
39 DRVL6 output Low-side gate driver output for BUCK6 controller, 5 V supply.
40 PGNDSNS6 power_in Power GND connection for BUCK6; connect to the ground terminal of the external low-side FET.
41 BOOT6 input Bootstrap pin for BUCK6 controller; connect a 100-nF ceramic capacitor between this pin and SW6.
42 SW6 input Switch node connection for BUCK6 controller.
43 DRVH6 output High-side gate driver output for BUCK6 controller, powered from VSYS + 5 V.
44 FBVOUT6 input Remote feedback sense for BUCK6 controller; connect to positive terminal of output capacitor.
45 ILIM6 input Current limit set pin for BUCK6 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
46 PVINVTT power_in Power supply to VTT LDO, VDDQ level; bypass with a 10-µF (minimum) ceramic capacitor and connect to ground when not in use.
47 VTT power_out Output of VTT LDO at VDDQ / 2; bypass with 2× 22-µF (minimum) ceramic capacitors and leave floating when not in use.
48 VTTFB input Remote feedback sense for VTT LDO at VDDQ / 2; connect to positive terminal of output capacitor and short to GND when not in use.
49 LDOA3 power_out Output of LDOA3, 0.7-1.5 V; bypass with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
50 PVINLDOA2_A3 power_in Power supply to LDOA2 and LDOA3 at 1.8 V; bypass with a 4.7-µF (typical) ceramic capacitor and connect to ground when not in use.
51 LDOA2 power_out Output of LDOA2, 0.7-1.5 V; bypass with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
52 AGND power_in Analog ground; do not connect to the thermal pad ground on the top layer, and connect to the ground of the VREF capacitor.
53 VREF power_out Band-gap reference output at 1.25 V; stabilize with a 100-nF (typical) ceramic capacitor to quiet ground.
54 LDO3P3 power_out Output of 3.3-V internal LDO; bypass to ground with a 4.7-µF (typical) ceramic capacitor.
55 VSYS power_in System voltage detection and input to internal LDOs (3.3 V and 5 V); bypass to ground with a 1-µF (typical) ceramic capacitor.
56 LDO5P0 power_out Output of 5-V internal LDO or internal switch to V5ANA; bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57 V5ANA input External 5-V supply input to the internal load switch connecting to LDO5P0; an optional bypass capacitor improves transient performance.
58 CLK input I2C clock input.
59 DATA bidirectional I2C data line.
60 THERMTRIPB input Thermal shutdown signal from SoC.
61 SLP_S0B input Power state pin; PMIC enters Connected Standby on falling edge and exits on rising edge.
62 SLP_S3B input Power state pin; PMIC enters S3 on falling edge and exits S3 into S0 on rising edge.
63 SLP_S4B input Power state pin; PMIC enters S4 on falling edge and exits S4 into S3 on rising edge.
64 ILIM2 input Current limit set pin for BUCK2 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(8x8)
Category Power Management (PMIC)
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VSYS input voltage from battery VSYS -0.3 28 V 8
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6 -0.3 7 V 8
SW1, SW2, SW6 SW1, SW2, SW6 -5 28 V 8
LX3, LX4, LX5 LX3, LX4, LX5 -2 8 V 8
DATA, CLK, PCH_PWROK, RSMRSTB, GPO -0.3 3.6 V 8
PMICEN, SLP_S4B, SLP_S3B, SLP_S0B, LDOLS_EN, SWA1_EN, THERMTRIPB, IRQB, PROCHOT -0.3 7 V 8
Storage temperature Tstg -55 150 °C 8
VSYS input voltage VSYS 5.6 13 21 V 8
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1 -0.3 5 5.5 V 8
Operating ambient temperature TA -40 27 85 °C 8
Operating junction temperature TJ -40 27 125 °C 8
Band-gap reference accuracy VREF -0.5 0.5 % 9
Band-gap output capacitor CVREF 0.047 0.1 0.22 µF 9
VSYS UVLO threshold for LDO5 VSYS_UVLO_5V 5.24 5.4 5.56 V VSYS falling 9
VSYS UVLO threshold for LDO3P3 VSYS_UVLO_3V 3.45 3.6 3.75 V VSYS falling 9
Critical threshold of die temperature TCRIT 130 145 160 °C TJ rising 9
Hot threshold of die temperature THOT 110 115 120 °C TJ rising 10
LDO5 DC output voltage VOUT 4.9 5 5.1 V IOUT = 10 mA 10
LDO5 external output capacitance COUT 2.7 4.7 10 µF 10
LDO3P3 DC output accuracy VOUT -3 3 % VIN = 13 V, IOUT = 10 mA 10
BUCK6 DC output voltage accuracy VOUT -2 2 % VOUT ≥ 1 V, IOUT = 100 mA to 7 A 13
BUCK6 low-side output valley current limit accuracy ILIM_LSD -15 15 % See Section 7.3.3.4, Current Limit, for details. 13
BUCK6 low-side current zero crossing detection threshold VTH_ZC -11 11 mV 13
BUCK6 source current out of ILIM6 pin ILIMREF 45 50 55 µA T = 25°C 13
BUCK6 voltage at ILIM6 pin VLIM 0.2 2.25 V VLIM = RLIM × ILIMREF 13
BUCK6 line regulation ΔVOUT/ΔVIN -0.5 0.5 % VOUT ≥ 1 V, IOUT = 7 A 13
BUCK6 load regulation ΔVOUT/ΔIOUT 0 1 % VIN = 13 V, VOUT ≥ 1 V, IOUT = 0 A to 7 A, referenced to VOUT at IOUT = 7 A 13
BUCK6 load transient regulation ΔVOUT_TR -5 5 % DC + AC at sense point, VIN = 13 V, VOUT = 1.35 V, IOUT = 2.1 A to 7 A and 7 A to 2.1 A with 1.96 µs of tr and tf (2.5 A/µs) 14
BUCK6 external output inductance LSW 0.376 0.47 0.564 µH 14
BUCK6 external output capacitance COUT 150 220 µF Recommended amount to meet transient specification 14
BUCK3 power input voltage VIN 4.5 5 5.5 V 14
BUCK3 DC output voltage accuracy VOUT -2 2 % VOUT = 1.05 V, IOUT = 1.5 A 14
BUCK3 DC output voltage accuracy VOUT -2.5 2.5 % VOUT = 1.05 V, IOUT = 100 mA 14
BUCK3 HSD FET current limit IIND_LIM 4.3 7 A 14
BUCK3 load regulation ΔVOUT/ΔIOUT -0.2 2 % VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A to 3 A, referenced to VOUT at IOUT = 1.5 A 15
BUCK3 load transient regulation ΔVOUT_TR -5 7 % DC + AC at sense point, VIN = 5 V, VOUT = 1.05 V, IOUT = 0.9 A to 3 A and 3 A to 0.9 A with slew rate of 2.5 A/µs 15
BUCK3 output filtering capacitance COUT 61.6 88 110 µF 15
BUCK3 input bypass capacitance CIN 2.5 10 12 µF 15
BUCK3 output inductance LSW 0.376 0.47 0.564 µH 15
BUCK4 power input voltage VIN 4.5 5 5.5 V 15
BUCK4 DC output voltage accuracy VOUT -2 2 % VOUT = 1.8 V, IOUT = 1.5 A 15
BUCK4 HSD FET current limit IIND_LIM 4.3 7 A 15
BUCK4 output filtering capacitance COUT 46 66 110 µF 16
BUCK5 load regulation ΔVOUT/ΔIOUT -0.2 1 % VIN = 5 V, VOUT = 1.24 V, IOUT = 0 A to 1.5 A, referenced to VOUT at IOUT = 0.75 A 16
BUCK5 output filtering capacitance COUT 31 44 110 µF 16
LDOA1 input voltage VIN 4.5 5 5.5 V 17
LDOA1 VOUT accuracy VOUT -2 2 % IOUT = 0 to 200 mA 17
LDOA1 load regulation ΔVOUT/ΔIOUT -2 2 % IOUT = 10 mA to 200 mA 17
LDOA1 external output capacitance COUT 2.7 4.7 10 µF 17
LDOA2 VOUT accuracy VOUT -2 3 % IOUT = 0 to 600 mA 18
LDOA2 overcurrent protection IOCP 0.65 1.25 A Measured with output shorted to ground 18
LDOA3 VOUT accuracy VOUT -2 3 % IOUT = 0 to 600 mA 19
LDOA3 overcurrent protection IOCP 0.65 1.25 A Measured with output shorted to ground 19
VTT DC output voltage accuracy VTT -10 10 mV Relative to VIN / 2, IOUT = 100 mA, 1.1 V ≤ VIN ≤ 1.5 V 20
VTT pulsed current (LPDDR3 and LPDDR4 OTPs) -500 500 mA source(+) and sink(-): LPDDR3 and LPDDR4 OTPs, 1.1 V ≤ VIN ≤ 1.5 V 20
VTT load regulation ΔVOUT/ΔIOUT -10 10 mV Relative to VIN / 2, IOUT ≤ 10 mA, 1.1 V ≤ VIN ≤ 1.5 V 20
VTT load transient regulation ΔVOUT_TR -5 5 % DC + AC at sense point, 1.1 V ≤ VIN ≤ 1.5 V, (IOUT = 0 to 350 mA and 350 mA to 0) AND (0 to -350 mA and -350 mA to 0) with 1 µs of rise and fall time, COUT = 40 µF 20
VTT overcurrent protection (OTPs with VTT ILIM = 0.95 A) IOCP 0.95 A Measured with output shorted to ground: OTPs with VTT ILIM = 0.95 A 20

CAD (KiCad official)

  • Symbol: TPS650945A0RSKR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: tps650945a0rskr-etched.step / tps650945a0rskr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650945a0rskr.step / tps650945a0rskr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (92 pp, sha256 62c4cc47b18e645c, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF