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TPS65086470RSKT

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Texas Instruments Power Management - Specialized, VQFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS65086470RSKT

Texas Instruments · Power Management - Specialized · VQFN-64-EP(8x8)

TPS65086470RSKT from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FBGND2 power_in Remote negative feedback sense for the BUCK2 controller; connect to the negative terminal of the output capacitor, or to ground when not in use.
2 FBVOUT2 input Remote positive feedback sense for the BUCK2 controller; connect to the positive terminal of the output capacitor, or to ground when not in use.
3 DRVH2 output High-side gate driver output for the BUCK2 controller; leave floating when not in use.
4 SW2 passive Switch node connection for the BUCK2 controller; connect to ground when not in use.
5 BOOT2 input Bootstrap pin for the BUCK2 controller; connect a 100nF ceramic capacitor between this pin and SW2, and leave floating when not in use.
6 PGNDSNS2 power_in Power GND connection for BUCK2; connect to the ground terminal of the external low-side FET, or to ground when not in use.
7 DRVL2 output Low-side gate driver output for the BUCK2 controller; leave floating when not in use.
8 DRV5V_2_A1 power_in 5V supply to the BUCK2 gate driver and LDOA1; bypass to ground with a 2.2µF (typical) ceramic capacitor.
9 LDOA1 power_out LDOA1 output; bypass to ground with a 4.7µF (typical) ceramic capacitor, and leave floating when not in use.
10 LX3 passive Switch node connection for the BUCK3 converter; leave floating when not in use.
11 PVIN3 power_in Power input to the BUCK3 converter; bypass to ground with a 10µF (typical) ceramic capacitor.
12 FB3 input Remote feedback sense for the BUCK3 converter; connect to the positive terminal of the output capacitor, or to ground when not in use.
13 CTL1 input Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
14 CTL6/SLPENB2 input Active-high VR enable pin, or when configured as active-low sleep enable, moves a chosen VR group into (L) or out of (H) sleep state with possibly different output voltages.
15 IRQB output Open-drain output interrupt pin; see section 7.13.4 (IRQ: PMIC Interrupt Register) for definitions.
16 GPO1 output General-purpose output configurable as open-drain or push-pull, reflecting Power Good status of selected VRs or controlled by an I2C register bit.
17 SWB1 power_out Output of load switch B1; bypass to ground with a 0.1µF (typical) ceramic capacitor, and leave floating when not in use.
18 PVINSWB1_B2 power_in Power supply to load switches B1 and B2; bypass to ground with a 1µF (typical) ceramic capacitor, and connect to ground when not in use.
19 SWB2 power_out Output of load switch B2; bypass to ground with a 0.1µF (typical) ceramic capacitor, and leave floating when not in use.
20 LX5 passive Switch node connection for the BUCK5 converter; leave floating when not in use.
21 PVIN5 power_in Power input to the BUCK5 converter; bypass to ground with a 10µF (typical) ceramic capacitor.
22 FB5 input Remote feedback sense for the BUCK5 converter; connect to the positive terminal of the output capacitor, or to ground when not in use.
23 FB4 input Remote feedback sense for the BUCK4 converter; connect to the positive terminal of the output capacitor, or to ground when not in use.
24 PVIN4 power_in Power input to the BUCK4 converter; bypass to ground with a 10µF (typical) ceramic capacitor.
25 LX4 passive Switch node connection for the BUCK4 converter; leave floating when not in use.
26 GPO2 output General-purpose output configurable as open-drain or push-pull, reflecting Power Good status of selected VRs or controlled by an I2C register bit.
27 GPO3 output General-purpose output configurable as open-drain or push-pull, reflecting Power Good status of selected VRs or controlled by an I2C register bit.
28 GPO4 output Open-drain output that reflects Power Good status of selected VRs or is controlled by an I2C register bit.
29 FBVOUT1 input Remote feedback sense for the BUCK1 controller; connect to the positive terminal of the output capacitor, or to ground when not in use.
30 ILIM1 input Current limit set pin for the BUCK1 controller; fit a resistor to ground to set the external low-side FET current limit, or connect to ground when not in use.
31 SWA1 power_out Output of load switch A1; bypass to ground with a 0.1µF (typical) ceramic capacitor, and leave floating when not in use.
32 PVINSWA1 power_in Power supply to load switch A1; bypass to ground with a 1µF (typical) ceramic capacitor, and connect to ground when not in use.
33 DRVH1 output High-side gate driver output for the BUCK1 controller; leave floating when not in use.
34 SW1 passive Switch node connection for the BUCK1 controller; connect to ground when not in use.
35 BOOT1 input Bootstrap pin for the BUCK1 controller; connect a 100nF ceramic capacitor between this pin and SW1, and leave floating when not in use.
36 PGNDSNS1 power_in Power GND connection for BUCK1; connect to the ground terminal of the external low-side FET, or to ground when not in use.
37 DRVL1 output Low-side gate driver output for the BUCK1 controller; leave floating when not in use.
38 DRV5V_1_6 power_in 5V supply to the BUCK1 and BUCK6 gate drivers; bypass to ground with a 2.2µF (typical) ceramic capacitor.
39 DRVL6 output Low-side gate driver output for the BUCK6 controller; leave floating when not in use.
40 PGNDSNS6 power_in Power GND connection for BUCK6; connect to the ground terminal of the external low-side FET, or to ground when not in use.
41 BOOT6 input Bootstrap pin for the BUCK6 controller; connect a 100nF ceramic capacitor between this pin and SW6, and leave floating when not in use.
42 SW6 passive Switch node connection for the BUCK6 controller; connect to ground when not in use.
43 DRVH6 output High-side gate driver output for the BUCK6 controller; leave floating when not in use.
44 FBVOUT6 input Remote feedback sense for the BUCK6 controller and reference for VTT LDO regulation; connect to the positive terminal of the output capacitor, or to ground when not in use.
45 ILIM6 input Current limit set pin for the BUCK6 controller; fit a resistor to ground to set the external low-side FET current limit, or connect to ground when not in use.
46 PVINVTT power_in Power supply to the VTT LDO; bypass to ground with a 10µF (minimum) ceramic capacitor.
47 VTT power_out Output of the VTT LDO; bypass to ground with 2× 22µF (minimum) ceramic capacitors, and leave floating when not in use.
48 VTTFB input Remote feedback sense for the VTT LDO; connect to the positive terminal of the output capacitor, or to ground when not in use.
49 LDOA3 power_out Output of LDOA3; bypass to ground with a 4.7µF (typical) ceramic capacitor, and leave floating when not in use.
50 PVINLDOA2_A3 power_in Power supply to LDOA2 and LDOA3; bypass to ground with a 4.7µF (typical) ceramic capacitor, and connect to ground when not in use.
51 LDOA2 power_out Output of LDOA2; bypass to ground with a 4.7µF (typical) ceramic capacitor, and leave floating when not in use.
52 AGND power_in Analog ground; do not connect to the thermal pad ground on the top layer, and connect to the ground of the VREF capacitor.
53 VREF power_in Band-gap reference output; stabilize with a 100nF (typical) ceramic capacitor between this pin and quiet ground.
54 LDO3P3 power_out Output of the 3.3V internal LDO; bypass to ground with a 4.7µF (typical) ceramic capacitor.
55 VSYS power_in System voltage detection and input to the internal 3.3V and 5V LDOs; bypass to ground with a 1µF (typical) ceramic capacitor.
56 LDO5P0 power_out Output of the 5V internal LDO or an internal switch connecting this pin to V5ANA; bypass to ground with a 4.7µF (typical) ceramic capacitor.
57 V5ANA power_in Bias for converters BUCK3, BUCK4 and BUCK5; must be the same supply as PVINx, and it has an internal load switch to LDO5P0 when 5V is used.
58 CLK input I2C clock input.
59 DATA bidirectional I2C data pin.
60 CTL2 input Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
61 CTL3/SLPENB1 input Active-high VR enable pin, or when configured as active-low sleep enable, moves a chosen VR group into (L) or out of (H) sleep state with possibly different output voltages.
62 CTL4 input Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
63 CTL5 input Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
64 ILIM2 input Current limit set pin for the BUCK2 controller; fit a resistor to ground to set the external low-side FET current limit, or connect to ground when BUCK2 is not in use.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(8x8)
Category Power Management (PMIC)
Pins 65

CAD (KiCad official)

  • Symbol: TPS65086470RSKT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: tps65086470rskt-etched.step / tps65086470rskt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65086470rskt.step / tps65086470rskt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (132 pp, sha256 c4e8c656d1a83a4a, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF