component
TPS6508641RSKR
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, VQFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS6508641RSKR
Texas Instruments · Power Management Specialized - PMIC · VQFN-64-EP(8x8)
TPS6508641RSKR from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FBGND2 | input | Remote negative feedback sense for the BUCK2 controller, connected to the negative terminal of the output capacitor, or to ground when not in use. |
| 2 | FBVOUT2 | input | Remote positive feedback sense for the BUCK2 controller, connected to the positive terminal of the output capacitor, or to ground when not in use. |
| 3 | DRVH2 | output | High-side gate driver output for the BUCK2 controller; leave floating when not in use. |
| 4 | SW2 | input | Switch node connection for the BUCK2 controller; connect to ground when not in use. |
| 5 | BOOT2 | input | Bootstrap pin for the BUCK2 controller, with a 100-nF ceramic capacitor to SW2; leave floating when not in use. |
| 6 | PGNDSNS2 | input | Power GND connection for BUCK2 to the ground terminal of the external low-side FET; connect to ground when not in use. |
| 7 | DRVL2 | output | Low-side gate driver output for the BUCK2 controller; leave floating when not in use. |
| 8 | DRV5V_2_A1 | power_in | 5-V supply to the BUCK2 gate driver and LDOA1, bypassed with a 2.2-µF (typical) ceramic capacitor and typically shorted on board to LDO5P0. |
| 9 | LDOA1 | power_out | LDOA1 output, bypassed with a 4.7-µF (typical) ceramic capacitor; leave floating when not in use. |
| 10 | LX3 | output | Switch node connection for the BUCK3 converter; leave floating when not in use. |
| 11 | PVIN3 | power_in | Power input to the BUCK3 converter, bypassed with a 10-µF (typical) ceramic capacitor. |
| 12 | FB3 | input | Remote feedback sense for the BUCK3 converter at the positive terminal of the output capacitor; connect to ground when not in use. |
| 13 | CTL1 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 14 | CTL6/SLPENB2 | input | Active-high VR enable pin, or when configured as active-low sleep enable, moves a chosen group of VRs into (L) or out of (H) sleep state. |
| 15 | IRQB | output | Open-drain interrupt output pin. |
| 16 | GPO1 | output | General purpose output configurable as open-drain or push-pull, reflecting Power Good of chosen VRs or controlled by an I2C register bit. |
| 17 | SWB1 | power_out | Output of load switch B1, bypassed with a 0.1-µF (typical) ceramic capacitor; leave floating when not in use. |
| 18 | PVINSWB1_B2 | power_in | Power supply to load switches B1 and B2, bypassed with a 1-µF (typical) ceramic capacitor; connect to ground when not in use. |
| 19 | SWB2 | power_out | Output of load switch B2, bypassed with a 0.1-µF (typical) ceramic capacitor; leave floating when not in use. |
| 20 | LX5 | output | Switch node connection for the BUCK5 converter; leave floating when not in use. |
| 21 | PVIN5 | power_in | Power input to the BUCK5 converter, bypassed with a 10-µF (typical) ceramic capacitor. |
| 22 | FB5 | input | Remote feedback sense for the BUCK5 converter at the positive terminal of the output capacitor; connect to ground when not in use. |
| 23 | FB4 | input | Remote feedback sense for the BUCK4 converter at the positive terminal of the output capacitor; connect to ground when not in use. |
| 24 | PVIN4 | power_in | Power input to the BUCK4 converter, bypassed with a 10-µF (typical) ceramic capacitor. |
| 25 | LX4 | output | Switch node connection for the BUCK4 converter; leave floating when not in use. |
| 26 | GPO2 | output | General purpose output configurable as open-drain or push-pull, reflecting Power Good of chosen VRs or controlled by an I2C register bit. |
| 27 | GPO3 | output | General purpose output configurable as open-drain or push-pull, reflecting Power Good of chosen VRs or controlled by an I2C register bit. |
| 28 | GPO4 | output | Open-drain output configurable to reflect Power Good of chosen VRs or be controlled by an I2C register bit. |
| 29 | FBVOUT1 | input | Remote feedback sense for the BUCK1 controller at the positive terminal of the output capacitor; connect to ground when not in use. |
| 30 | ILIM1 | input | Current limit set pin for the BUCK1 controller, with a resistor to ground setting the low-side FET current limit; connect to ground when BUCK1 is not in use. |
| 31 | SWA1 | power_out | Output of load switch A1, bypassed with a 0.1-µF (typical) ceramic capacitor; leave floating when not in use. |
| 32 | PVINSWA1 | power_in | Power supply to load switch A1, bypassed with a 1-µF (typical) ceramic capacitor; connect to ground when not in use. |
| 33 | DRVH1 | output | High-side gate driver output for the BUCK1 controller; leave floating when not in use. |
| 34 | SW1 | input | Switch node connection for the BUCK1 controller; connect to ground when not in use. |
| 35 | BOOT1 | input | Bootstrap pin for the BUCK1 controller, with a 100-nF ceramic capacitor to SW1; leave floating when not in use. |
| 36 | PGNDSNS1 | input | Power GND connection for BUCK1 to the ground terminal of the external low-side FET; connect to ground when not in use. |
| 37 | DRVL1 | output | Low-side gate driver output for the BUCK1 controller; leave floating when not in use. |
| 38 | DRV5V_1_6 | power_in | 5-V supply to the BUCK1 and BUCK6 gate drivers, bypassed with a 2.2-µF (typical) ceramic capacitor and typically shorted on board to LDO5P0. |
| 39 | DRVL6 | output | Low-side gate driver output for the BUCK6 controller; leave floating when not in use. |
| 40 | PGNDSNS6 | input | Power GND connection for BUCK6 to the ground terminal of the external low-side FET; connect to ground when not in use. |
| 41 | BOOT6 | input | Bootstrap pin for the BUCK6 controller, with a 100-nF ceramic capacitor to SW6; leave floating when not in use. |
| 42 | SW6 | input | Switch node connection for the BUCK6 controller; connect to ground when not in use. |
| 43 | DRVH6 | output | High-side gate driver output for the BUCK6 controller; leave floating when not in use. |
| 44 | FBVOUT6 | input | Remote feedback sense for the BUCK6 controller and reference voltage for VTT LDO regulation; connect to ground when not in use. |
| 45 | ILIM6 | input | Current limit set pin for the BUCK6 controller, with a resistor to ground setting the low-side FET current limit; connect to ground when BUCK6 is not in use. |
| 46 | PVINVTT | power_in | Power supply to the VTT LDO, bypassed with a 10-µF (minimum) ceramic capacitor. |
| 47 | VTT | power_out | Output of the VTT LDO, bypassed with 2× 22-µF (minimum) ceramic capacitors; leave floating when not in use. |
| 48 | VTTFB | input | Remote feedback sense for the VTT LDO at the positive terminal of the output capacitor; connect to ground when not in use. |
| 49 | LDOA3 | power_out | Output of LDOA3, bypassed with a 4.7-µF (typical) ceramic capacitor; leave floating when not in use. |
| 50 | PVINLDOA2_A3 | power_in | Power supply to LDOA2 and LDOA3, bypassed with a 4.7-µF (typical) ceramic capacitor; connect to ground when not in use. |
| 51 | LDOA2 | power_out | Output of LDOA2, bypassed with a 4.7-µF (typical) ceramic capacitor; leave floating when not in use. |
| 52 | AGND | power_in | Analog ground, not to be connected to the thermal pad ground on the top layer, and connected to the ground of the VREF capacitor. |
| 53 | VREF | power_out | Band-gap reference output, stabilized with a 100-nF (typical) ceramic capacitor to quiet ground. |
| 54 | LDO3P3 | power_out | Output of the 3.3-V internal LDO, bypassed with a 4.7-µF (typical) ceramic capacitor. |
| 55 | VSYS | power_in | System voltage detection and input to the internal 3.3-V and 5-V LDOs, bypassed with a 1-µF (typical) ceramic capacitor. |
| 56 | LDO5P0 | power_out | Output of the 5-V internal LDO or of an internal switch connecting this pin to V5ANA, bypassed with a 4.7-µF (typical) ceramic capacitor. |
| 57 | V5ANA | power_in | Bias used by BUCK3, BUCK4 and BUCK5 for regulation, which must be the same supply as PVINx, with an internal switch to LDO5P0 when 5 V is used. |
| 58 | CLK | input | I2C clock input. |
| 59 | DATA | bidirectional | I2C data line. |
| 60 | CTL2 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 61 | CTL3/SLPENB1 | input | Active-high VR enable pin, or when configured as active-low sleep enable, moves a chosen group of VRs into (L) or out of (H) sleep state. |
| 62 | CTL4 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 63 | CTL5 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 64 | ILIM2 | input | Current limit set pin for the BUCK2 controller, with a resistor to ground setting the low-side FET current limit; connect to ground when BUCK2 is not in use. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(8x8) |
| Category | Power Supply Chip |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage from battery | VSYS | -0.3 | 28 | V | 9 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 9 | ||
| V5ANA voltage | V5ANA | -0.3 | 6 | V | 9 | ||
| HBM ESD | VESD | -1000 | 1000 | V | Human Body Model, ANSI/ESDA/JEDEC JS001 | 9 | |
| CDM ESD | VESD | -250 | 250 | V | Charged Device Model, JESD22-C101 | 9 | |
| VSYS operating | VSYS | 5.6 | 13 | 21 | V | 10 | |
| Operating ambient temperature | TA | -40 | 27 | 85 | °C | 10 | |
| Operating junction temperature | TJ | -40 | 27 | 125 | °C | 10 | |
| Junction-to-ambient thermal resistance | RθJA | 25.8 | °C/W | RSK (VQFN) 64 pins | 10 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 11.3 | °C/W | 10 | |||
| Junction-to-board thermal resistance | RθJB | 4.4 | °C/W | 10 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.7 | °C/W | 10 | |||
| VREF accuracy | VREF | -0.5 | 0.5 | % | Band-gap reference, typ 1.25 V | 11 | |
| Band-gap output capacitor | CVREF | 0.047 | 0.1 | 0.22 | µF | 11 | |
| VSYS UVLO threshold for LDO5 | VSYS_UVLO_5V | 5.24 | 5.4 | 5.56 | V | VSYS falling | 11 |
| VSYS UVLO threshold for LDO3P3 | VSYS_UVLO_3V | 3.45 | 3.6 | 3.75 | V | VSYS falling | 11 |
| Critical die temperature threshold | TCRIT | 130 | 145 | 160 | °C | TJ rising | 11 |
| Hot die temperature threshold | THOT | 110 | 115 | 120 | °C | TJ rising | 11 |
| LDO5 DC output voltage | VOUT | 4.9 | 5 | 5.1 | V | IOUT = 10 mA | 11 |
| LDO5 input voltage at VSYS | VIN | 5.6 | 13 | 21 | V | 11 | |
| LDO5 external output capacitance | COUT | 2.7 | 4.7 | 10 | µF | 11 | |
| LDO3P3 accuracy | VOUT | -3 | 3 | % | VIN = 13 V, IOUT = 10 mA | 11 | |
| LDO3P3 external output capacitance | COUT | 2.2 | 4.7 | 10 | µF | 12 | |
| Buck controller power input voltage | VIN | 5.6 | 13 | 21 | V | BUCK1, BUCK2, BUCK6 | 12 |
| Buck controller DC output accuracy | -2 | 2 | % | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 100 mA to 7 A | 12 | ||
| Buck controller feedback regulation voltage | VFB_EXT_BUCK1 | 384 | 400 | 416 | mV | Buck1 programmed for external feedback | 12 |
| Source current out of ILIM1 pin | ILIMREF | 45 | 50 | 55 | µA | T = 25°C | 12 |
| Buck controller line regulation | ΔVOUT/ΔVIN | -0.5 | 0.5 | % | IOUT = 7 A | 12 | |
| Buck converter input voltage | VIN | 3 | 5.5 | V | BUCK3, BUCK4, BUCK5 | 13 | |
| Buck converter DC output accuracy | -2 | 2 | % | VIN = 5.0 V, IOUT = 1.5 A | 13 | ||
| Buck converter HSD FET current limit | IIND_LIM | 4.3 | 7 | A | 13 | ||
| Buck converter continuous DC output current | IOUT | 3 | A | 13 | |||
| LDOA1 input voltage | VIN | 4.5 | 5 | 5.5 | V | 14 | |
| LDOA1 accuracy | VOUT | -2 | 2 | % | IOUT = 0 to 200 mA | 14 | |
| LDOA2/A3 accuracy | VOUT | -2 | 3 | % | IOUT = 0 to 600 mA | 14 | |
| LDOA2/A3 input voltage | VIN | 1.8 | 1.98 | V | VOUT + VDROP; minimum must be ≥ 1.62 V | 14 | |
| LDOA2/A3 overcurrent protection | IOCP | 0.65 | 1.25 | A | Output shorted to ground | 14 | |
| VTT LDO input voltage | VIN | 1.2 | 3.3 | V | 15 | ||
| VTT DC output accuracy | -25 | 25 | mV | Relative to VIN / 2, IOUT ≤ 500 mA, 1.1 V ≤ VIN ≤ 1.35 V | 15 | ||
| VTT DC output current | IOUT | -500 | 0 | 500 | mA | 1.1 V ≤ VIN ≤ 1.5 V | 15 |
| SWA1 input voltage range | VIN | 0.5 | 3.3 | V | 16 | ||
| SWA1 RDSON | RDSON | 60 | 93 | mΩ | VIN = 1.8 V, at IOUT = IOUT(MAX) | 16 | |
| SWB RDSON | RDSON | 68 | 92 | mΩ | VIN = 1.8 V, per output switch | 16 | |
| Operating junction temperature range note: I2C low-level input | VIL | 0.4 | V | 17 | |||
| I2C high-level input voltage | VIH | 1.2 | V | 17 | |||
| CTLx high-level input voltage | VIH | 0.85 | V | 17 | |||
| IRQB/GPOx low-level output voltage | VOL | 0.4 | V | IOL < 2 mA | 17 |
CAD (KiCad official)
- Symbol:
TPS6508641RSKR - Footprint:
Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm - 3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
tps6508641rskr-etched.step/tps6508641rskr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps6508641rskr.step/tps6508641rskr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (129 pp, sha256
3beed246bb3805cb, retrieved 2026-10-23, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).