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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS6508640RSKR

Texas Instruments · Power Management - Specialized · VQFN-64-EP(8x8)

TPS6508640RSKR from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FBGND2	power_in	Remote negative feedback sense for BUCK2 controller; connect to negative terminal of output capacitor or ground when not in use.
2	FBVOUT2	input	Remote positive feedback sense for BUCK2 controller; connect to positive terminal of output capacitor or ground when not in use.
3	DRVH2	output	High-side gate driver output for BUCK2 controller; leave floating when not in use.
4	SW2	input	Switch node connection for BUCK2 controller; connect to ground when not in use.
5	BOOT2	input	Bootstrap pin for BUCK2 controller; connect 100nF ceramic capacitor between this pin and SW2 pin.
6	PGNDSNS2	input	Power GND connection for BUCK2; connect to ground terminal of external low-side FET or ground when not in use.
7	DRVL2	output	Low-side gate driver output for BUCK2 controller; leave floating when not in use.
8	DRV5V_2_A1	power_in	5V supply to BUCK2 gate driver and LDOA1; bypass to ground with 2.2µF ceramic capacitor.
9	LDOA1	power_out	LDOA1 regulated output voltage from 1.35V to 3.3V; bypass to ground with 4.7µF ceramic capacitor.
10	LX3	input	Switch node connection for BUCK3 converter; leave floating when not in use.
11	PVIN3	power_in	Power input to BUCK3 converter from 3V to 5.5V; bypass to ground with 10µF ceramic capacitor.
12	FB3	input	Remote feedback sense for BUCK3 converter; connect to positive terminal of output capacitor or ground when not in use.
13	CTL1	input	Active-high VR enable pin; groups of voltage regulators can be assigned to enable at assertion or disable at deassertion.
14	CTL6/SLPENB2	input	Active-high VR enable pin or active-low sleep enable pin; groups of VRs can enter sleep state with different output voltage.
15	IRQB	output	Open-drain output interrupt pin; asserted on power fault or die temperature exceeding TCRIT threshold.
16	GPO1	output	General purpose output configured as open-drain or push-pull; reflects Power Good status or I2C-controlled logic level.
17	SWB1	output	Output of load switch B1 rated for 400mA; bypass to ground with 0.1µF ceramic capacitor when not in use.
18	PVINSWB1_B2	power_in	Power supply to load switches B1 and B2 from 0.5V to 3.3V; bypass to ground with 1µF ceramic capacitor.
19	SWB2	output	Output of load switch B2 rated for 400mA; bypass to ground with 0.1µF ceramic capacitor when not in use.
20	LX5	input	Switch node connection for BUCK5 converter; leave floating when not in use.
21	PVIN5	power_in	Power input to BUCK5 converter from 3V to 5.5V; bypass to ground with 10µF ceramic capacitor.
22	FB5	input	Remote feedback sense for BUCK5 converter; connect to positive terminal of output capacitor or ground when not in use.
23	FB4	input	Remote feedback sense for BUCK4 converter; connect to positive terminal of output capacitor or ground when not in use.
24	PVIN4	power_in	Power input to BUCK4 converter from 3V to 5.5V; bypass to ground with 10µF ceramic capacitor.
25	LX4	input	Switch node connection for BUCK4 converter; leave floating when not in use.
26	GPO2	output	General purpose output configured as open-drain or push-pull; reflects Power Good status or I2C-controlled logic level.
27	GPO3	output	General purpose output configured as open-drain or push-pull; reflects Power Good status or I2C-controlled logic level.
28	GPO4	output	Open-drain output reflecting Power Good status of assigned VRs or controlled by I2C register bit.
29	FBVOUT1	input	Remote feedback sense for BUCK1 controller; connect to positive terminal of output capacitor or ground when not in use.
30	ILIM1	input	Current limit set pin for BUCK1 controller; fit a resistor from this pin to ground to set external FET current limit.
31	SWA1	output	Output of load switch A1 rated for 300mA; bypass to ground with 0.1µF ceramic capacitor when not in use.
32	PVINSWA1	power_in	Power supply to load switch A1 from 0.5V to 3.3V; bypass to ground with 1µF ceramic capacitor.
33	DRVH1	output	High-side gate driver output for BUCK1 controller; leave floating when not in use.
34	SW1	input	Switch node connection for BUCK1 controller; connect to ground when not in use.
35	BOOT1	input	Bootstrap pin for BUCK1 controller; connect 100nF ceramic capacitor between this pin and SW1 pin.
36	PGNDSNS1	input	Power GND connection for BUCK1; connect to ground terminal of external low-side FET or ground when not in use.
37	DRVL1	output	Low-side gate driver output for BUCK1 controller; leave floating when not in use.
38	DRV5V_1_6	power_in	5V supply to BUCK1 and BUCK6 gate drivers; bypass to ground with 2.2µF ceramic capacitor.
39	DRVL6	output	Low-side gate driver output for BUCK6 controller; leave floating when not in use.
40	PGNDSNS6	input	Power GND connection for BUCK6; connect to ground terminal of external low-side FET or ground when not in use.
41	BOOT6	input	Bootstrap pin for BUCK6 controller; connect 100nF ceramic capacitor between this pin and SW6 pin.
42	SW6	input	Switch node connection for BUCK6 controller; connect to ground when not in use.
43	DRVH6	output	High-side gate driver output for BUCK6 controller; leave floating when not in use.
44	FBVOUT6	input	Remote feedback sense for BUCK6 controller and reference voltage for VTT LDO regulation; connect to capacitor output or ground when not in use.
45	ILIM6	input	Current limit set pin for BUCK6 controller; fit a resistor from this pin to ground to set external FET current limit.
46	PVINVTT	power_in	Power supply to VTT LDO from 1.2V to 3.3V; bypass to ground with 10µF minimum ceramic capacitor.
47	VTT	power_out	VTT LDO output for DDR termination, sourcing or sinking up to ±500mA; bypass to ground with 2×22µF minimum capacitors.
48	VTTFB	input	Remote feedback sense for VTT LDO; connect to positive terminal of output capacitor or ground when not in use.
49	LDOA3	power_out	LDOA3 regulated output voltage from 0.7V to 1.5V at up to 600mA; bypass to ground with 4.7µF ceramic capacitor.
50	PVINLDOA2_A3	power_in	Power supply to LDOA2 and LDOA3 from 1.62V to 1.98V; bypass to ground with 4.7µF ceramic capacitor.
51	LDOA2	power_out	LDOA2 regulated output voltage from 0.7V to 1.5V at up to 600mA; bypass to ground with 4.7µF ceramic capacitor.
52	AGND	power_in	Analog ground reference point; do not connect to thermal pad ground on top layer, connect to ground of VREF capacitor.
53	VREF	power_out	Bandgap reference output of 1.25V; stabilize by connecting 100nF ceramic capacitor between this pin and quiet ground.
54	LDO3P3	power_out	3.3V internal LDO output; bypass to ground with 4.7µF ceramic capacitor.
55	VSYS	power_in	System voltage detection and input to internal LDOs from 5.6V to 21V; bypass to ground with 1µF ceramic capacitor.
56	LDO5P0	power_out	5V internal LDO output or internal switch that connects to V5ANA; bypass to ground with 4.7µF ceramic capacitor.
57	V5ANA	power_out	5V bias used by converters BUCK3, BUCK4, BUCK5 for regulation; must be same supply as PVINx pins.
58	CLK	input	I2C serial clock input supporting standard (100kHz), fast (400kHz), and fast mode plus (1MHz) operation.
59	DATA	bidirectional	I2C serial data open-drain bidirectional pin supporting standard (100kHz), fast (400kHz), and fast mode plus (1MHz) operation.
60	CTL2	input	Active-high VR enable pin; groups of voltage regulators can be assigned to enable at assertion or disable at deassertion.
61	CTL3/SLPENB1	input	Active-high VR enable pin or active-low sleep enable pin; groups of VRs can enter sleep state with different output voltage.
62	CTL4	input	Active-high VR enable pin; groups of voltage regulators can be assigned to enable at assertion or disable at deassertion.
63	CTL5	input	Active-high VR enable pin; groups of voltage regulators can be assigned to enable at assertion or disable at deassertion.
64	ILIM2	input	Current limit set pin for BUCK2 controller; fit a resistor from this pin to ground to set external FET current limit.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(8x8)
Category	Power Management (PMIC)
Pins	65

CAD (KiCad official)

Symbol: TPS6508640RSKR
Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)
3D model files: tps6508640rskr-etched.step / tps6508640rskr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps6508640rskr.step / tps6508640rskr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (132 pp, sha256 c4e8c656d1a83a4a, retrieved 2026-09-27, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF