# TPS650860A0RSKR

**Texas Instruments** · Power Management - Specialized · VQFN-64(8x8)

TPS650860A0RSKR from Texas Instruments, in a VQFN-64(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FBGND2 | input | Remote negative feedback sense for the BUCK2 controller; connect to the negative terminal of the output capacitor. |
| 2 | FBVOUT2 | input | Remote positive feedback sense for the BUCK2 controller; connect to the positive terminal of the output capacitor. |
| 3 | DRVH2 | output | High-side gate driver output for the BUCK2 controller. |
| 4 | SW2 | input | Switch node connection for the BUCK2 controller. |
| 5 | BOOT2 | input | Bootstrap pin for the BUCK2 controller; connect a 100-nF ceramic capacitor between this pin and SW2. |
| 6 | PGNDSNS2 | power_in | Power GND connection for BUCK2; connect to the ground terminal of the external low-side FET. |
| 7 | DRVL2 | output | Low-side gate driver output for the BUCK2 controller. |
| 8 | DRV5V_2_A1 | power_in | 5-V supply to the BUCK2 gate driver and LDOA1; bypass to ground with a 2.2-µF (TYP) ceramic capacitor; typically shorted on board to LDO5P0. |
| 9 | LDOA1 | power_out | LDOA1 output; bypass to ground with a 4.7-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 10 | LX3 | output | Switch node connection for the BUCK3 converter. |
| 11 | PVIN3 | power_in | Power input to the BUCK3 converter; bypass to ground with a 10-µF (TYP) ceramic capacitor. |
| 12 | FB3 | input | Remote feedback sense for the BUCK3 converter; connect to the positive terminal of the output capacitor. |
| 13 | CTL1 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 14 | CTL6/SLPENB2 | input | Active-high VR enable pin, or when configured as active-low sleep enable, places a chosen group of VRs into (L) or out of (H) sleep state where output voltages may differ from normal state. |
| 15 | IRQB | output | Open-drain output interrupt pin; refer to Section 5.9.3 for definitions. |
| 16 | GPO1 | output | General-purpose output configurable as open-drain or push-pull, programmed to reflect power good of selected VRs or controlled by an I2C register bit used as an external VR enable. |
| 17 | SWB1 | power_out | Output of load switch B1; bypass to ground with a 0.1-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 18 | PVINSWB1_B2 | power_in | Power supply to load switches B1 and B2; bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance; connect to ground when not in use. |
| 19 | SWB2 | power_out | Output of load switch B2; bypass to ground with a 0.1-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 20 | LX5 | output | Switch node connection for the BUCK5 converter. |
| 21 | PVIN5 | power_in | Power input to the BUCK5 converter; bypass to ground with a 10-µF (TYP) ceramic capacitor. |
| 22 | FB5 | input | Remote feedback sense for the BUCK5 converter; connect to the positive terminal of the output capacitor. |
| 23 | FB4 | input | Remote feedback sense for the BUCK4 converter; connect to the positive terminal of the output capacitor. |
| 24 | PVIN4 | power_in | Power input to the BUCK4 converter; bypass to ground with a 10-µF (TYP) ceramic capacitor. |
| 25 | LX4 | output | Switch node connection for the BUCK4 converter. |
| 26 | GPO2 | output | General-purpose output configurable as open-drain or push-pull, programmed to reflect power good of selected VRs or controlled by an I2C register bit used as an external VR enable. |
| 27 | GPO3 | output | General-purpose output configurable as open-drain or push-pull, programmed to reflect power good of selected VRs or controlled by an I2C register bit used as an external VR enable. |
| 28 | GPO4 | output | Open-drain general-purpose output programmed to reflect power good of selected VRs or controlled by an I2C register bit used as an external VR enable. |
| 29 | FBVOUT1 | input | Remote feedback sense for the BUCK1 controller; connect to the positive terminal of the output capacitor. |
| 30 | ILIM1 | input | Current limit set pin for the BUCK1 controller; a resistor from this pin to ground sets the current limit of the external low-side FET. |
| 31 | SWA1 | power_out | Output of load switch A1; bypass to ground with a 0.1-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 32 | PVINSWA1 | power_in | Power supply to load switch A1; bypass to ground with a 1-µF (TYP) ceramic capacitor to improve transient performance; connect to ground when not in use. |
| 33 | DRVH1 | output | High-side gate driver output for the BUCK1 controller. |
| 34 | SW1 | input | Switch node connection for the BUCK1 controller. |
| 35 | BOOT1 | input | Bootstrap pin for the BUCK1 controller; connect a 100-nF ceramic capacitor between this pin and SW1. |
| 36 | PGNDSNS1 | power_in | Power GND connection for BUCK1; connect to the ground terminal of the external low-side FET. |
| 37 | DRVL1 | output | Low-side gate driver output for the BUCK1 controller. |
| 38 | DRV5V_1_6 | power_in | 5-V supply to the BUCK1 and BUCK6 gate drivers; bypass to ground with a 2.2-µF (TYP) ceramic capacitor; typically shorted on board to LDO5P0. |
| 39 | DRVL6 | output | Low-side gate driver output for the BUCK6 controller. |
| 40 | PGNDSNS6 | power_in | Power GND connection for BUCK6; connect to the ground terminal of the external low-side FET. |
| 41 | BOOT6 | input | Bootstrap pin for the BUCK6 controller; connect a 100-nF ceramic capacitor between this pin and SW6. |
| 42 | SW6 | input | Switch node connection for the BUCK6 controller. |
| 43 | DRVH6 | output | High-side gate driver output for the BUCK6 controller. |
| 44 | FBVOUT6 | input | Remote feedback sense for the BUCK6 controller; connect to the positive terminal of the output capacitor. |
| 45 | ILIM6 | input | Current limit set pin for the BUCK6 controller; a resistor from this pin to ground sets the current limit of the external low-side FET. |
| 46 | PVINVTT | power_in | Power supply to the VTT LDO; bypass to ground with a 10-µF (MIN) ceramic capacitor. |
| 47 | VTT | power_out | Output of the VTT LDO; bypass to ground with 2× 22-µF (MIN) ceramic capacitors. |
| 48 | VTTFB | input | Remote feedback sense for the VTT LDO; connect to the positive terminal of the output capacitor. |
| 49 | LDOA3 | power_out | Output of LDOA3; bypass to ground with a 4.7-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 50 | PVINLDOA2_A3 | power_in | Power supply to LDOA2 and LDOA3; bypass to ground with a 4.7-µF (TYP) ceramic capacitor; connect to ground when not in use. |
| 51 | LDOA2 | power_out | Output of LDOA2; bypass to ground with a 4.7-µF (TYP) ceramic capacitor; leave floating when not in use. |
| 52 | AGND | power_in | Analog ground; do not connect to the thermal pad ground on the top layer; connect to the ground of the VREF capacitor. |
| 53 | VREF | power_out | Band-gap reference output; stabilize by connecting a 100-nF (TYP) ceramic capacitor between this pin and quiet ground. |
| 54 | LDO3P3 | power_out | Output of the 3.3-V internal LDO; bypass to ground with a 4.7-µF (TYP) ceramic capacitor. |
| 55 | VSYS | power_in | System voltage detection and input to the internal LDOs (3.3 V and 5 V); bypass to ground with a 1-µF (TYP) ceramic capacitor. |
| 56 | LDO5P0 | power_out | Output of the 5-V internal LDO or an internal switch connecting this pin to V5ANA; bypass to ground with a 4.7-µF (TYP) ceramic capacitor. |
| 57 | V5ANA | power_in | External 5-V supply input to the internal load switch that connects this pin to LDO5P0; an optional ceramic bypass capacitor improves transient performance. |
| 58 | CLK | input | I2C clock input. |
| 59 | DATA | bidirectional | I2C data pin. |
| 60 | CTL2 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 61 | CTL3/SLPENB1 | input | Active-high VR enable pin, or when configured as active-low sleep enable, places a chosen group of VRs into (L) or out of (H) sleep state where output voltages may differ from normal state. |
| 62 | CTL4 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 63 | CTL5 | input | Active-high VR enable pin; a group of VRs can be assigned to be enabled at assertion or disabled at deassertion. |
| 64 | ILIM2 | input | Current limit set pin for the BUCK2 controller; a resistor from this pin to ground sets the current limit of the external low-side FET. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64(8x8) |
| Category | Power Management (PMIC) |
| Pins | 65 |

## CAD (KiCad official)

- Symbol: `TPS650860A0RSKR`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm`
- 3D model: VQFN-64(8x8) (KiCad packages3D, STEP)
- 3D model files: `tps650860a0rskr-etched.step` / `tps650860a0rskr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps650860a0rskr.step` / `tps650860a0rskr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65086) (95 pp, sha256 `b7cfeeb441054f14`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps650860a0rskr-datasheet.pdf)