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TPS65072RSLR
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# TPS65072RSLR++**Texas Instruments** · Power Management Specialized - PMIC · VQFN-48-EP(6x6)++TPS65072RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AVDD6 | power_out | Internal always-on voltage output; connect a 4.7 µF capacitor from AVDD6 to GND. |+| 2 | VLDO2 | power_out | Output voltage of LDO2, with a stated output range of 0.8 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor. |+| 3 | VINLDO1/2 | power_in | Input voltage for LDO1 and LDO2, with a stated range of 1.8 V to 6.3 V (or VSYS if lower) and a 2.2 µF input capacitor. |+| 4 | VLDO1 | power_out | Output voltage of LDO1, with a stated output range of 0.9 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor. |+| 5 | BAT | power_out | Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin. |+| 6 | BAT | power_out | Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin. |+| 7 | SYS | power_out | System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin. |+| 8 | SYS | power_out | System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin. |+| 9 | ISET | input | Connect a resistor from this pin to GND to set the charge current. |+| 10 | AC | power_in | Input power for the power path manager, connected to an external DC supply with a stated input range of 4.3 V to 17 V, input current up to 2.5 A and at least 1 µF to GND. |+| 11 | TS | input | Temperature sense input for an NTC thermistor on the battery pack; the default setting is a 10 kΩ NTC, with 100 kΩ NTC selectable. |+| 12 | USB | power_in | Input power for the power path manager from a USB port with a stated input range of 4.3 V to 17 V and input current up to 1.3 A; default input current limit is 500 mA maximum and at least 1 µF to GND is required. |+| 13 | POWER_ON | input | Power_ON input for the internal state machine that must be pulled HIGH by the application processor to keep the system on after PB_IN is released; if released LOW, the DCDC converters and LDOs turn off when PB_IN is HIGH. |+| 14 | EN_DCDC1 | input | Active-high enable input for DCDC1. |+| 15 | EN_DCDC2 | input | Active-high enable input for DCDC2. |+| 16 | EN_DCDC3 | input | Active-high enable input for DCDC3. |+| 17 | DEFDCDC3 | input | Select pin for the DCDC3 output voltage. |+| 18 | DEFDCDC2 | input | Select pin for the DCDC2 output voltage. |+| 19 | VDCDC1 | input | Feedback voltage sense input; for the fixed-voltage option it connects directly to Vout1, and for the adjustable version it connects to an external resistor divider, with an output range of 0.6 V to VINDCDC1. |+| 20 | L1 | output | Switch pin for DCDC1; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current. |+| 21 | VINDCDC1/2 | power_in | Input voltage for the DCDC1 and DCDC2 step-down converters; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V. |+| 22 | L2 | output | Switch pin for DCDC2; connect to the inductor (1.5 µH to 2.2 µH recommended), with 1500 mA maximum output current. |+| 23 | VDCDC2 | input | Feedback voltage sense input; connect directly to Vout2, with an output range of 0.6 V to VINDCDC2. |+| 24 | PB_OUT | output | Open-drain output driven by the status of /PB_IN after debounce; it goes LOW when PB_IN is LOW. |+| 25 | PB_IN | input | Enable input; when pulled LOW the DCDC converters and LDOs start with the internally programmed sequencing, with an internal 50 kΩ pull-up to AVDD6. |+| 26 | PGOOD | output | Open-drain power-good output whose delay equals the reset setting, going low per PGOODMASK and also driven LOW for 0.5 ms when PB_IN is pulled LOW for more than 15 s. |+| 27 | SDAT | bidirectional | Data line for the I2C interface. |+| 28 | SCLK | input | Clock input for the I2C interface. |+| 29 | VDCDC3 | input | Feedback voltage sense input; connect directly to Vout3, with an output range of 0.6 V to VINDCDC2. |+| 30 | PGND3 | power_in | Power ground for DCDC3; connect to PGND (thermal pad). |+| 31 | L3 | output | Switch pin for DCDC3; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current for TPS65072. |+| 32 | VIN_DCDC3 | power_in | Input voltage for the DCDC3 step-down converter; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V. |+| 33 | ISINK2 | input | Input to current sink 2; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V. |+| 34 | ISINK1 | input | Input to current sink 1; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V. |+| 35 | ISET1 (AD_IN6) | input | Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 1; it is also analog input 6 of the A/D converter. |+| 36 | ISET2 (AD_IN7) | input | Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 0; it is also analog input 7 of the A/D converter. |+| 37 | L4 | input | Switch pin of the white LED boost converter; connect to the inductor and rectifier diode, with an absolute maximum voltage of 40 V and a 22 µH inductor. |+| 38 | FB_WLED | input | Feedback input for the boost converter output voltage, with an absolute maximum of 40 V. |+| 39 | EN_EXTLDO | output | TPS65072 only: active-high push-pull output that enables an external LDO, set and reset by the programmed sequencing option and pulled to SYS when HIGH. |+| 40 | INT | output | Open-drain interrupt output, generated by AC or USB voltage applied or removed and by PB_IN being pulled low (optionally high); the touch-screen event source does not apply to TPS65072. |+| 41 | BYPASS | output | Connect a 10 µF bypass capacitor to GND; this pin can optionally serve as a 2.26 V reference output with a maximum load of 0.1 mA. |+| 42 | AGND | power_in | Analog ground; connect to PGND (thermal pad). |+| 43 | AD_IN1 (TSX1) | input | Analog input 1 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072. |+| 44 | AD_IN2 (TSX2) | input | Analog input 2 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072. |+| 45 | AD_IN3 (TSY1) | input | Analog input 3 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072. |+| 46 | AD_IN4 (TSY2) | input | Analog input 4 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072. |+| 47 | EN_wLED | input | Active-high enable input for the wLED driver; the converter is enabled by the ENABLE ISINK bit or by this pin. |+| 48 | INT_LDO | output | Connect a 2.2 µF bypass capacitor from this pin to GND; the pin is the output of an internal LDO that powers the touch-screen controller (TSREF), which TPS65072 does not provide. |+| 49 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(6x6) |+| Category | Power Supply Chip |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPS65072RSLR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm`+- 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps65072rslr-etched.step` / `tps65072rslr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps65072rslr.step` / `tps65072rslr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65073) (100 pp, sha256 `a79405797feebece`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps65072rslr-datasheet.pdf)
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connect a 4.7 µF capacitor from AVDD6 to GND."+ },+ {+ "number": "2",+ "name": "VLDO2",+ "type": "power_out",+ "description": "Output voltage of LDO2, with a stated output range of 0.8 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor."+ },+ {+ "number": "3",+ "name": "VINLDO1/2",+ "type": "power_in",+ "description": "Input voltage for LDO1 and LDO2, with a stated range of 1.8 V to 6.3 V (or VSYS if lower) and a 2.2 µF input capacitor."+ },+ {+ "number": "4",+ "name": "VLDO1",+ "type": "power_out",+ "description": "Output voltage of LDO1, with a stated output range of 0.9 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor."+ },+ {+ "number": "5",+ "name": "BAT",+ "type": "power_out",+ "description": "Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin."+ },+ {+ "number": "6",+ "name": "BAT",+ "type": "power_out",+ "description": "Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin."+ },+ {+ "number": "7",+ "name": "SYS",+ "type": "power_out",+ "description": "System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin."+ },+ {+ "number": "8",+ "name": "SYS",+ "type": "power_out",+ "description": "System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin."+ },+ {+ "number": "9",+ "name": "ISET",+ "type": "input",+ "description": "Connect a resistor from this pin to GND to set the charge current."+ },+ {+ "number": "10",+ "name": "AC",+ "type": "power_in",+ "description": "Input power for the power path manager, connected to an external DC supply with a stated input range of 4.3 V to 17 V, input current up to 2.5 A and at least 1 µF to GND."+ },+ {+ "number": "11",+ "name": "TS",+ "type": "input",+ "description": "Temperature sense input for an NTC thermistor on the battery pack; the default setting is a 10 kΩ NTC, with 100 kΩ NTC selectable."+ },+ {+ "number": "12",+ "name": "USB",+ "type": "power_in",+ "description": "Input power for the power path manager from a USB port with a stated input range of 4.3 V to 17 V and input current up to 1.3 A; default input current limit is 500 mA maximum and at least 1 µF to GND is required."+ },+ {+ "number": "13",+ "name": "POWER_ON",+ "type": "input",+ "description": "Power_ON input for the internal state machine that must be pulled HIGH by the application processor to keep the system on after PB_IN is released; if released LOW, the DCDC converters and LDOs turn off when PB_IN is HIGH."+ },+ {+ "number": "14",+ "name": "EN_DCDC1",+ "type": "input",+ "description": "Active-high enable input for DCDC1."+ },+ {+ "number": "15",+ "name": "EN_DCDC2",+ "type": "input",+ "description": "Active-high enable input for DCDC2."+ },+ {+ "number": "16",+ "name": "EN_DCDC3",+ "type": "input",+ "description": "Active-high enable input for DCDC3."+ },+ {+ "number": "17",+ "name": "DEFDCDC3",+ "type": "input",+ "description": "Select pin for the DCDC3 output voltage."+ },+ {+ "number": "18",+ "name": "DEFDCDC2",+ "type": "input",+ "description": "Select pin for the DCDC2 output voltage."+ },+ {+ "number": "19",+ "name": "VDCDC1",+ "type": "input",+ "description": "Feedback voltage sense input; for the fixed-voltage option it connects directly to Vout1, and for the adjustable version it connects to an external resistor divider, with an output range of 0.6 V to VINDCDC1."+ },+ {+ "number": "20",+ "name": "L1",+ "type": "output",+ "description": "Switch pin for DCDC1; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current."+ },+ {+ "number": "21",+ "name": "VINDCDC1/2",+ "type": "power_in",+ "description": "Input voltage for the DCDC1 and DCDC2 step-down converters; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V."+ },+ {+ "number": "22",+ "name": "L2",+ "type": "output",+ "description": "Switch pin for DCDC2; connect to the inductor (1.5 µH to 2.2 µH recommended), with 1500 mA maximum output current."+ },+ {+ "number": "23",+ "name": "VDCDC2",+ "type": "input",+ "description": "Feedback voltage sense input; connect directly to Vout2, with an output range of 0.6 V to VINDCDC2."+ },+ {+ "number": "24",+ "name": "PB_OUT",+ "type": "output",+ "description": "Open-drain output driven by the status of /PB_IN after debounce; it goes LOW when PB_IN is LOW."+ },+ {+ "number": "25",+ "name": "PB_IN",+ "type": "input",+ "description": "Enable input; when pulled LOW the DCDC converters and LDOs start with the internally programmed sequencing, with an internal 50 kΩ pull-up to AVDD6."+ },+ {+ "number": "26",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good output whose delay equals the reset setting, going low per PGOODMASK and also driven LOW for 0.5 ms when PB_IN is pulled LOW for more than 15 s."+ },+ {+ "number": "27",+ "name": "SDAT",+ "type": "bidirectional",+ "description": "Data line for the I2C interface."+ },+ {+ "number": "28",+ "name": "SCLK",+ "type": "input",+ "description": "Clock input for the I2C interface."+ },+ {+ "number": "29",+ "name": "VDCDC3",+ "type": "input",+ "description": "Feedback voltage sense input; connect directly to Vout3, with an output range of 0.6 V to VINDCDC2."+ },+ {+ "number": "30",+ "name": "PGND3",+ "type": "power_in",+ "description": "Power ground for DCDC3; connect to PGND (thermal pad)."+ },+ {+ "number": "31",+ "name": "L3",+ "type": "output",+ "description": "Switch pin for DCDC3; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current for TPS65072."+ },+ {+ "number": "32",+ "name": "VIN_DCDC3",+ "type": "power_in",+ "description": "Input voltage for the DCDC3 step-down converter; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V."+ },+ {+ "number": "33",+ "name": "ISINK2",+ "type": "input",+ "description": "Input to current sink 2; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V."+ },+ {+ "number": "34",+ "name": "ISINK1",+ "type": "input",+ "description": "Input to current sink 1; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V."+ },+ {+ "number": "35",+ "name": "ISET1 (AD_IN6)",+ "type": "input",+ "description": "Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 1; it is also analog input 6 of the A/D converter."+ },+ {+ "number": "36",+ "name": "ISET2 (AD_IN7)",+ "type": "input",+ "description": "Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 0; it is also analog input 7 of the A/D converter."+ },+ {+ "number": "37",+ "name": "L4",+ "type": "input",+ "description": "Switch pin of the white LED boost converter; connect to the inductor and rectifier diode, with an absolute maximum voltage of 40 V and a 22 µH inductor."+ },+ {+ "number": "38",+ "name": "FB_WLED",+ "type": "input",+ "description": "Feedback input for the boost converter output voltage, with an absolute maximum of 40 V."+ },+ {+ "number": "39",+ "name": "EN_EXTLDO",+ "type": "output",+ "description": "TPS65072 only: active-high push-pull output that enables an external LDO, set and reset by the programmed sequencing option and pulled to SYS when HIGH."+ },+ {+ "number": "40",+ "name": "INT",+ "type": "output",+ "description": "Open-drain interrupt output, generated by AC or USB voltage applied or removed and by PB_IN being pulled low (optionally high); the touch-screen event source does not apply to TPS65072."+ },+ {+ "number": "41",+ "name": "BYPASS",+ "type": "output",+ "description": "Connect a 10 µF bypass capacitor to GND; this pin can optionally serve as a 2.26 V reference output with a maximum load of 0.1 mA."+ },+ {+ "number": "42",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to PGND (thermal pad)."+ },+ {+ "number": "43",+ "name": "AD_IN1 (TSX1)",+ "type": "input",+ "description": "Analog input 1 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072."+ },+ {+ "number": "44",+ "name": "AD_IN2 (TSX2)",+ "type": "input",+ "description": "Analog input 2 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072."+ },+ {+ "number": "45",+ "name": "AD_IN3 (TSY1)",+ "type": "input",+ "description": "Analog input 3 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072."+ },+ {+ "number": "46",+ "name": "AD_IN4 (TSY2)",+ "type": "input",+ "description": "Analog input 4 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072."+ },+ {+ "number": "47",+ "name": "EN_wLED",+ "type": "input",+ "description": "Active-high enable input for the wLED driver; the converter is enabled by the ENABLE ISINK bit or by this pin."+ },+ {+ "number": "48",+ "name": "INT_LDO",+ "type": "output",+ "description": "Connect a 2.2 µF bypass capacitor from this pin to GND; the pin is the output of an internal LDO that powers the touch-screen controller (TSREF), which TPS65072 does not provide."+ },+ {+ "number": "49",+ "name": "Thermal Pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The thermal pad is a separate exposed pad with no numbered pin; it is listed in the datasheet as the; Pin 39 and pin 47 differ between device variants. The TPS65072 column gives EN_EXTLDO on pin 39 and ; Device Options lists TPS65072 with no touch-screen controller, yet the shared pin table still descri",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.1335,+ "at": "2026-10-08T19:22:44"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps65073",+ "pages": 100,+ "sha256": "a79405797feebece",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps65072rslr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9f2bee3e90403c6e9c4ac64a128ac3152a91b65170b30b4e20bf37dd09da6212",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps65072rslr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e894028c4c1835bbb42f7602f18d0ecfa92962e1a9312b9d06042333400dac83",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}