component
TPS65072RSLR
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65072RSLR
Texas Instruments · Power Management Specialized - PMIC · VQFN-48-EP(6x6)
TPS65072RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD6 | power_out | Internal always-on voltage output; connect a 4.7 µF capacitor from AVDD6 to GND. |
| 2 | VLDO2 | power_out | Output voltage of LDO2, with a stated output range of 0.8 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor. |
| 3 | VINLDO1/2 | power_in | Input voltage for LDO1 and LDO2, with a stated range of 1.8 V to 6.3 V (or VSYS if lower) and a 2.2 µF input capacitor. |
| 4 | VLDO1 | power_out | Output voltage of LDO1, with a stated output range of 0.9 V to 3.3 V, a maximum output current of 100 mA and a 2.2 µF output capacitor. |
| 5 | BAT | power_out | Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin. |
| 6 | BAT | power_out | Charger power stage output connected to the battery; place a 10 µF ceramic capacitor from these pins to GND, with a stated current of up to 2 A at this pin. |
| 7 | SYS | power_out | System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin. |
| 8 | SYS | power_out | System voltage output of the power path manager from which all voltage regulators are typically powered; use 22 µF to 100 µF at this pin. |
| 9 | ISET | input | Connect a resistor from this pin to GND to set the charge current. |
| 10 | AC | power_in | Input power for the power path manager, connected to an external DC supply with a stated input range of 4.3 V to 17 V, input current up to 2.5 A and at least 1 µF to GND. |
| 11 | TS | input | Temperature sense input for an NTC thermistor on the battery pack; the default setting is a 10 kΩ NTC, with 100 kΩ NTC selectable. |
| 12 | USB | power_in | Input power for the power path manager from a USB port with a stated input range of 4.3 V to 17 V and input current up to 1.3 A; default input current limit is 500 mA maximum and at least 1 µF to GND is required. |
| 13 | POWER_ON | input | Power_ON input for the internal state machine that must be pulled HIGH by the application processor to keep the system on after PB_IN is released; if released LOW, the DCDC converters and LDOs turn off when PB_IN is HIGH. |
| 14 | EN_DCDC1 | input | Active-high enable input for DCDC1. |
| 15 | EN_DCDC2 | input | Active-high enable input for DCDC2. |
| 16 | EN_DCDC3 | input | Active-high enable input for DCDC3. |
| 17 | DEFDCDC3 | input | Select pin for the DCDC3 output voltage. |
| 18 | DEFDCDC2 | input | Select pin for the DCDC2 output voltage. |
| 19 | VDCDC1 | input | Feedback voltage sense input; for the fixed-voltage option it connects directly to Vout1, and for the adjustable version it connects to an external resistor divider, with an output range of 0.6 V to VINDCDC1. |
| 20 | L1 | output | Switch pin for DCDC1; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current. |
| 21 | VINDCDC1/2 | power_in | Input voltage for the DCDC1 and DCDC2 step-down converters; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V. |
| 22 | L2 | output | Switch pin for DCDC2; connect to the inductor (1.5 µH to 2.2 µH recommended), with 1500 mA maximum output current. |
| 23 | VDCDC2 | input | Feedback voltage sense input; connect directly to Vout2, with an output range of 0.6 V to VINDCDC2. |
| 24 | PB_OUT | output | Open-drain output driven by the status of /PB_IN after debounce; it goes LOW when PB_IN is LOW. |
| 25 | PB_IN | input | Enable input; when pulled LOW the DCDC converters and LDOs start with the internally programmed sequencing, with an internal 50 kΩ pull-up to AVDD6. |
| 26 | PGOOD | output | Open-drain power-good output whose delay equals the reset setting, going low per PGOODMASK and also driven LOW for 0.5 ms when PB_IN is pulled LOW for more than 15 s. |
| 27 | SDAT | bidirectional | Data line for the I2C interface. |
| 28 | SCLK | input | Clock input for the I2C interface. |
| 29 | VDCDC3 | input | Feedback voltage sense input; connect directly to Vout3, with an output range of 0.6 V to VINDCDC2. |
| 30 | PGND3 | power_in | Power ground for DCDC3; connect to PGND (thermal pad). |
| 31 | L3 | output | Switch pin for DCDC3; connect to the inductor (1.5 µH to 2.2 µH recommended), with 600 mA maximum output current for TPS65072. |
| 32 | VIN_DCDC3 | power_in | Input voltage for the DCDC3 step-down converter; this pin must be connected to SYS, with a stated range of 2.8 V to 6.3 V. |
| 33 | ISINK2 | input | Input to current sink 2; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V. |
| 34 | ISINK1 | input | Input to current sink 1; connect the LED cathodes to this pin, with up to 25 mA per string and an absolute maximum of 20 V. |
| 35 | ISET1 (AD_IN6) | input | Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 1; it is also analog input 6 of the A/D converter. |
| 36 | ISET2 (AD_IN7) | input | Connect a resistor from this pin to GND to set the full-scale current for ISINK1 and ISINK2 when the current-level bit in WLED_CTRL0 is 0; it is also analog input 7 of the A/D converter. |
| 37 | L4 | input | Switch pin of the white LED boost converter; connect to the inductor and rectifier diode, with an absolute maximum voltage of 40 V and a 22 µH inductor. |
| 38 | FB_WLED | input | Feedback input for the boost converter output voltage, with an absolute maximum of 40 V. |
| 39 | EN_EXTLDO | output | TPS65072 only: active-high push-pull output that enables an external LDO, set and reset by the programmed sequencing option and pulled to SYS when HIGH. |
| 40 | INT | output | Open-drain interrupt output, generated by AC or USB voltage applied or removed and by PB_IN being pulled low (optionally high); the touch-screen event source does not apply to TPS65072. |
| 41 | BYPASS | output | Connect a 10 µF bypass capacitor to GND; this pin can optionally serve as a 2.26 V reference output with a maximum load of 0.1 mA. |
| 42 | AGND | power_in | Analog ground; connect to PGND (thermal pad). |
| 43 | AD_IN1 (TSX1) | input | Analog input 1 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072. |
| 44 | AD_IN2 (TSX2) | input | Analog input 2 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen x-plate function is not available on TPS65072. |
| 45 | AD_IN3 (TSY1) | input | Analog input 3 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072. |
| 46 | AD_IN4 (TSY2) | input | Analog input 4 for the A/D converter with an absolute maximum of 3.3 V to AGND; the touch-screen y-plate function is not available on TPS65072. |
| 47 | EN_wLED | input | Active-high enable input for the wLED driver; the converter is enabled by the ENABLE ISINK bit or by this pin. |
| 48 | INT_LDO | output | Connect a 2.2 µF bypass capacitor from this pin to GND; the pin is the output of an internal LDO that powers the touch-screen controller (TSREF), which TPS65072 does not provide. |
| 49 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(6x6) |
| Category | Power Supply Chip |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TPS65072RSLR - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm - 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps65072rslr-etched.step/tps65072rslr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65072rslr.step/tps65072rslr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (100 pp, sha256
a79405797feebece, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).