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TPS65070RSLT

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Texas Instruments Battery Management, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps65070rsltfactory-2.0.0extractor-text
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Datasheet

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Contents

README

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TPS65070RSLT

Texas Instruments · Battery Management · VQFN-48-EP(6x6)

TPS65070RSLT from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD6 power_out Internal always-on voltage supply; connect a 4.7 µF capacitor to GND.
2 VLDO2 power_out LDO2 regulated output voltage.
3 VINLDO1/2 power_in Input voltage for LDO1 and LDO2; operating range 1.8 V to 6.3 V.
4 VLDO1 power_out LDO1 regulated output voltage.
5 BAT power_out Charger power stage output connected to battery; place a 10 µF ceramic capacitor to GND.
6 BAT power_out Charger power stage output connected to battery; place a 10 µF ceramic capacitor to GND.
7 SYS power_out System voltage output from power path manager; powers all voltage regulators.
8 SYS power_out System voltage output from power path manager; powers all voltage regulators.
9 ISET input Charge current setting input; connect resistor to GND to set charge current.
10 AC power_in AC power input for power path manager, operating range 4.3 V to 17 V; connect 1 µF minimum capacitor to GND.
11 TS input Battery temperature sense input for NTC thermistor; supports 10-kΩ or 100-kΩ curves.
12 USB power_in USB power input for power path manager, operating range 4.3 V to 17 V with default 500 mA current limit; connect 1 µF minimum capacitor to GND.
13 POWER_ON input Power-ON state machine input; pull high to maintain system ON after PB_IN release.
14 EN_DCDC1 input DCDC1 converter enable input, active high.
15 EN_DCDC2 input DCDC2 converter enable input, active high.
16 EN_DCDC3 input DCDC3 converter enable input, active high.
17 DEFDCDC3 input DCDC3 output voltage selection input.
18 DEFDCDC2 input DCDC2 output voltage selection input.
19 VDCDC1 input DCDC1 feedback voltage sense input; connect directly to output or to external resistor divider.
20 L1 output DCDC1 inductor switch node; connect to external inductor.
21 VINDCDC1/2 power_in Input voltage for DCDC1 and DCDC2 converters, must be connected to SYS pin.
22 L2 output DCDC2 inductor switch node; connect to external inductor.
23 VDCDC2 input DCDC2 feedback voltage sense input; connect directly to output.
24 PB_OUT output Open-drain power button output driven by debounced PB_IN status.
25 PB_IN input Power button enable input with internal 50 kΩ pull-up to AVDD6; pull low to start converters and LDOs.
26 PGOOD output Open-drain power good output with delay time equal to reset delay setting.
27 SDAT bidirectional I2C data line, open-drain bidirectional.
28 SCLK input I2C clock input.
29 VDCDC3 input DCDC3 feedback voltage sense input; connect directly to output.
30 PGND3 power_in DCDC3 power ground; connect to PGND (thermal pad).
31 L3 output DCDC3 inductor switch node; connect to external inductor.
32 VIN_DCDC3 power_in Input voltage for DCDC3 converter, must be connected to SYS pin.
33 ISINK2 input LED current sink 2 input; connect cathode of LEDs.
34 ISINK1 input LED current sink 1 input; connect cathode of LEDs.
35 ISET1 input Current level full-scale setting input for ISINK1 and ISINK2 when WLED_CTRL0 bit is set to 1; also ADC input 6.
36 ISET2 input Current level full-scale setting input for ISINK1 and ISINK2 when WLED_CTRL0 bit is set to 0; also ADC input 7.
37 L4 tri_state wLED boost converter inductor switch node; connect to external inductor and rectifier diode.
38 FB_WLED input wLED boost converter output voltage feedback input.
39 RESET output Open-drain active-low reset output; reset delay equals register PGOOD setting; status depends on THRESHOLD voltage.
40 INT output Open-drain interrupt output; triggered by touch screen contact, AC/USB voltage changes, or PB_IN activity.
41 BYPASS power_out Bypass capacitor pin; connect 10 µF capacitor to GND; optional reference output 2.26 V with maximum load 0.1 mA.
42 AGND power_in Analog ground; connect to PGND (thermal pad).
43 AD_IN1 input ADC input 1; for TPS65070 also serves as touch screen x-plate input 1.
44 AD_IN2 input ADC input 2; for TPS65070 also serves as touch screen x-plate input 2.
45 AD_IN3 input ADC input 3; for TPS65070 also serves as touch screen y-plate input 1.
46 AD_IN4 input ADC input 4; for TPS65070 also serves as touch screen y-plate input 2.
47 THRESHOLD input Reset comparator threshold input; RESET goes low if voltage drops below 1 V.
48 INT_LDO power_out Internal LDO output for touch screen controller (TSREF); connect 2.2 µF capacitor to GND.
49 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(6x6)
Category Power Management (PMIC)
Pins 49

CAD (KiCad official)

  • Symbol: TPS65070RSLT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps65070rslt-etched.step / tps65070rslt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65070rslt.step / tps65070rslt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (100 pp, sha256 a79405797feebece, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF