component

TPS65050RSMR

Public Made by Adom

by adom

Texas Instruments Power Management Specialized - PMIC, VQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chiptps65050rsmrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 18d ago
viewers tps65050rsmr: viewers · Ray 18d ago
package.json Publish 0.1.0 · Ray 18d ago
page.json Set visibility: public · Ray 18d ago
README.md Initial commit: component/tps65050rsmr · Ray 18d ago
tps65050rsmr-etched.glb tps65050rsmr: factory component page (tier=lcsc) · Ray 18d ago
tps65050rsmr-etched.step tps65050rsmr: factory component page (tier=lcsc) · Ray 18d ago
tps65050rsmr-hero.glb tps65050rsmr: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
tps65050rsmr-hero.overlay.json Publish 0.1.0 · Ray 18d ago
tps65050rsmr.glb Publish 0.1.0 · Ray 18d ago
tps65050rsmr.kicad_mod Publish 0.1.0 · Ray 18d ago
tps65050rsmr.kicad_sym Publish 0.1.0 · Ray 18d ago
tps65050rsmr.lbr Publish 0.1.0 · Ray 18d ago
tps65050rsmr.step Publish 0.1.0 · Ray 18d ago

TPS65050RSMR

Texas Instruments · Power Management Specialized - PMIC · VQFN-32-EP(4x4)

TPS65050RSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BP input Input for the bypass capacitor of the internal reference.
2 AGND power_in Analog ground; connect to PGND and the thermal pad.
3 VCC power_in Power supply for the digital and analog circuitry of DCDC1, DCDC2 and the LDOs; must be connected to the same voltage supply as VINDCDC1/2.
4 VINLDO2 input Input voltage for LDO2, recommended range 1.5 V to 6.5 V.
5 VLDO2 output Output voltage of LDO2; LDO1/LDO2 output current is rated up to 400 mA and output range 1 V to 3.6 V.
6 DEFLDO2 input Digital input used to set the default output voltage of LDO1 to LDO4.
7 PB_IN input Input for the pushbutton ON-OFF function; pulling it high toggles PB_OUT.
8 GND power_in Ground; connect to GND.
9 DEFLDO3 input Digital input used to set the default output voltage of LDO1 to LDO4.
10 VLDO3 output Output voltage of LDO3; output current is rated up to 200 mA.
11 VINLDO3/4 input Input voltage for LDO3 and LDO4, recommended range 1.5 V to 6.5 V.
12 VLDO4 output Output voltage of LDO4; output current is rated up to 200 mA.
13 DEFLDO4 input Digital input used to set the default output voltage of LDO1 to LDO4; MSB.
14 PB_OUT output Open-drain output, active low after VCC exceeds the undervoltage lockout threshold.
15 EN_LDO3 input Enable input for LDO3; logic high enables the LDO and logic low disables it.
16 EN_LDO4 input Enable input for LDO4; logic high enables the LDO and logic low disables it.
17 DEFDCDC2 input On the TPS65050, feedback pin for converter 2; connect to the center of the external resistor divider.
18 VDCDC2 input Feedback voltage sense input for converter 2; connect directly to the converter 2 output.
19 PGND2 power_in Power ground for converter 2.
20 L2 output Switch pin of converter 2, connected to the inductor.
21 VINDCDC1/2 input Input voltage for the VDCDC1 and VDCDC2 step-down converters, recommended range 2.5 V to 6 V; must be connected to the same supply as VCC.
22 L1 output Switch pin of converter 1, connected to the inductor.
23 PGND1 power_in Power ground for converter 1.
24 FB_DCDC1 input Feedback input to set the converter 1 output voltage between 0.6 V and VI; connect the external resistor divider between VOUT1, this pin and GND.
25 EN_DCDC1 input Enable input for converter 1, active high.
26 EN_DCDC2 input Enable input for converter 2, active high.
27 EN_LDO1 input Enable input for LDO1; logic high enables the LDO and logic low disables it.
28 EN_LDO2 input Enable input for LDO2; logic high enables the LDO and logic low disables it.
29 VINLDO1 input Input voltage for LDO1, recommended range 1.5 V to 6.5 V.
30 VLDO1 output Output voltage of LDO1; output current is rated up to 400 mA.
31 DEFLDO1 input Digital input used to set the default output voltage of LDO1 to LDO4; LSB.
32 MODE input Selects Power Save Mode (low) or forced PWM mode (high) for DCDC1 and DCDC2.
33 Thermal pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(4x4)
Category Power Supply Chip
Pins 33

CAD (KiCad official)

  • Symbol: TPS65050RSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps65050rsmr-etched.step / tps65050rsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65050rsmr.step / tps65050rsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 2d98e1f35d04a8b6, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF