component
TPS650250RHBR
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS650250RHBR
Texas Instruments · Battery Management · VQFN-32-EP(5x5)
TPS650250RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDCDC3 | input | VDCDC3 feedback voltage sense input; connect directly to VDCDC3 output. |
| 2 | PGND3 | power_in | Power ground for VDCDC3 converter. |
| 3 | L3 | passive | Switch pin of VDCDC3 converter; VDCDC3 inductor connects here. |
| 4 | VINDCDC3 | power_in | Input voltage for VDCDC3 step-down converter (2.5V to 6V range); must be connected to same voltage supply as VINDCDC1, VINDCDC2, and VCC. |
| 5 | VINDCDC1 | power_in | Input voltage for VDCDC1 step-down converter (2.5V to 6V range); must be connected to same voltage supply as VINDCDC2, VINDCDC3, and VCC. |
| 6 | L1 | passive | Switch pin of VDCDC1 converter; VDCDC1 inductor connects here. |
| 7 | PGND1 | power_in | Power ground for VDCDC1 converter. |
| 8 | VDCDC1 | input | VDCDC1 feedback voltage sense input; connect directly to VDCDC1 output. |
| 9 | DEFDCDC1 | input | Input signal indicating default VDCDC1 voltage: 0 = 2.8V, 1 = 3.3V; can also connect to resistor divider between VDCDC1 and GND for output voltage range 0.6V to VINDCDC1. |
| 10 | FB_LDO2 | input | Feedback pin for LDO2. |
| 11 | FB_LDO1 | input | Feedback pin for LDO1. |
| 12 | Vdd_alive | output | Output voltage for Vdd_alive LDO (30 mA, 1.0V nominal). |
| 13 | AGND2 | power_in | Analog ground connection; all analog ground pins are connected internally on the chip. |
| 14 | VLDO2 | output | Output voltage of LDO2 (200 mA maximum, 1V to 3.3V range). |
| 15 | VINLDO | power_in | Input voltage for LDO1 and LDO2 (1.5V to 6.5V range). |
| 16 | VLDO1 | output | Output voltage of LDO1 (200 mA maximum, 1V to 3.3V range). |
| 17 | EN_LDO | input | Enable input for LDO1 and LDO2; logic high enables the LDOs, logic low disables the LDOs. |
| 18 | EN_DCDC3 | input | VDCDC3 enable pin; logic high enables the regulator, logic low disables the regulator. |
| 19 | EN_DCDC2 | input | VDCDC2 enable pin; logic high enables the regulator, logic low disables the regulator. |
| 20 | EN_DCDC1 | input | VDCDC1 enable pin; logic high enables the regulator, logic low disables the regulator. |
| 21 | PWRFAIL | output | Open-drain output, active low when PWRFAIL comparator indicates low VBAT condition. |
| 22 | DEFDCDC2 | input | Input signal indicating default VDCDC2 voltage: 0 = 1.8V, 1 = 2.5V; can also connect to resistor divider between VDCDC2 and GND for output voltage range 0.6V to VINDCDC2. |
| 23 | MODE | input | Select between Power Safe Mode (low level, PFM at light load) and forced PWM mode (high level) for DCDC1, DCDC2, and DCDC3. |
| 24 | EN_Vdd_alive | input | Enable input for Vdd_alive LDO; logic high enables the LDO, logic low disables the LDO. |
| 25 | VDCDC2 | input | VDCDC2 feedback voltage sense input; connect directly to VDCDC2 output. |
| 26 | PGND2 | power_in | Power ground for VDCDC2 converter. |
| 27 | L2 | passive | Switch pin of VDCDC2 converter; VDCDC2 inductor connects here. |
| 28 | VINDCDC2 | power_in | Input voltage for VDCDC2 step-down converter (2.5V to 6V range); must be connected to same voltage supply as VINDCDC1, VINDCDC3, and VCC. |
| 29 | Vcc | power_in | Power supply for digital and analog circuitry of DCDC1, DCDC2, and DCDC3 DC-DC converters; must be connected to same voltage supply as VINDCDC1, VINDCDC2, and VINDCDC3. |
| 30 | PWRFAIL_SNS | input | Input for the comparator driving the PWRFAIL output. |
| 31 | AGND1 | power_in | Analog ground connection; all analog ground pins are connected internally on the chip. |
| 32 | DEFDCDC3 | input | This pin must be connected to a resistor divider between VDCDC3 and GND; output voltage of DCDC3 converter can be set in range from 0.6V to VINDCDC3. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
TPS650250RHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps650250rhbr-etched.step/tps650250rhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps650250rhbr.step/tps650250rhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
d0e751af73007df4, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).