component
TPS650250QRHBRQ1
Public Made by Adomby adom
Texas Instruments Battery Management ICs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS650250QRHBRQ1
Texas Instruments · Battery Management ICs · VQFN-32-EP(5x5)
TPS650250QRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDCDC3 | input | VDCDC3 feedback voltage sense input, connect directly to VDCDC3. |
| 2 | PGND3 | power_in | Power ground for VDCDC3 converter. |
| 3 | L3 | output | Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. |
| 4 | VINDCDC3 | power_in | Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2 and VCC. |
| 5 | VINDCDC1 | power_in | Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3 and VCC. |
| 6 | L1 | output | Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. |
| 7 | PGND1 | power_in | Power ground for VDCDC1 converter. |
| 8 | VDCDC1 | input | VDCDC1 feedback voltage sense input, connect directly to VDCDC1. |
| 9 | DEFDCDC1 | input | Input signal indicating default VDCDC1 voltage, 0 = 2.8V, 1 = 3.3V. This pin can also be connected to a resistor divider between VDCDC1 and GND to set the output from 0.6V to VINDCDC1. |
| 10 | FB_LDO2 | input | Feedback pin for LDO2. |
| 11 | FB_LDO1 | input | Feedback pin for LDO1. |
| 12 | Vdd_alive | power_out | Output voltage for Vdd_alive, 1 V output of the 30 mA LDO. |
| 13 | AGND2 | power_in | Analog ground connection. All analog ground pins are connected internally on the chip. |
| 14 | VLDO2 | power_out | Output voltage of LDO2. |
| 15 | VINLDO | power_in | Input voltage for LDO1 and LDO2. LDOs operate with input voltages between 1.5V and 6.5V. |
| 16 | VLDO1 | power_out | Output voltage of LDO1. |
| 17 | EN_LDO | input | Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs. |
| 18 | EN_DCDC3 | input | VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
| 19 | EN_DCDC2 | input | VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
| 20 | EN_DCDC1 | input | VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
| 21 | PWRFAIL | output | Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. |
| 22 | DEFDCDC2 | input | Input signal indicating default VDCDC2 voltage, 0 = 1.8V, 1 = 2.5V. This pin can also be connected to a resistor divider between VDCDC2 and GND to set the output from 0.6V to VINDCDC2. |
| 23 | MODE | input | Selects between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. High level selects forced PWM Mode, low level selects Power Safe Mode. |
| 24 | EN_Vdd_alive | input | Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO. |
| 25 | VDCDC2 | input | VDCDC2 feedback voltage sense input, connect directly to VDCDC2. |
| 26 | PGND2 | power_in | Power ground for VDCDC2 converter. |
| 27 | L2 | output | Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. |
| 28 | VINDCDC2 | power_in | Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3 and VCC. |
| 29 | Vcc | power_in | Power supply for digital and analog circuitry of DCDC1, DCDC2 and DCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1 and VINDCDC2. |
| 30 | PWRFAIL_SNS | input | Input for the comparator driving the /PWRFAIL output. The input is compared to a 1V threshold (falling edge). |
| 31 | AGND1 | power_in | Analog ground connection. All analog ground pins are connected internally on the chip. |
| 32 | DEFDCDC3 | input | Input that must be connected to a resistor divider between VDCDC3 and GND to set the DCDC3 output from 0.6V to VINDCDC3. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management ICs |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range on all pins except A/PGND pins with respect to AGND | -0.3 | 7 | V | 3 | |||
| Voltage range on pins VLDO1, VLDO2, FB_LDO1, FB_LDO2 | -0.3 | 3.6 | V | 3 | |||
| Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 | 2000 | mA | 3 | ||||
| Peak current at all other pins | 500 | mA | 3 | ||||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Input voltage range step-down converters | VCC | 2.5 | 6 | V | VINDCDC1, VINDCDC2, VINDCDC3 | 4 | |
| Output voltage range for LDOs | VO | 1 | 3.3 | V | 4 | ||
| Input voltage range for LDOs | VI | 1.5 | 6.5 | V | VINLDO1, VINLDO2 | 4 | |
| Output current at L1, VDCDC1 | IO | 1600 | mA | 4 | |||
| Output current at L2, VDCDC2 | IO | 800 | mA | 4 | |||
| Output current at L3, VDCDC3 | IO | 800 | mA | 4 | |||
| Output current at VLDO1, VLDO2 | IO | 200 | mA | 4 | |||
| Output current at Vdd_alive | IO | 30 | mA | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering | RCC | 1 | 10 | Ω | 4 | ||
| High level input voltage | VIH | 1.45 | V | EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE; max is VCC | 5 | ||
| Low level input voltage | VIL | 0 | 0.4 | V | EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE | 5 | |
| Input bias current | IH | 0.01 | 0.1 | mA | Control signals | 5 | |
| Operating quiescent current PFM, all 3 DCDC converters enabled, zero load, no switching, LDOs enabled | I(qPFM) | 135 | 170 | mA | VCC = 3.6V | 5 | |
| Operating quiescent current PFM, all 3 DCDC converters enabled, zero load, no switching, LDO1, LDO2 = OFF, Vdd_alive = ON | I(qPFM) | 75 | 100 | mA | VCC = 3.6V | 5 | |
| Current into VCC, PWM: DCDC1 and DCDC2 enabled and running in PWM, LDOs off | IVCC(PWM) | 1.5 | 2.5 | mA | VCC = 3.6V | 5 | |
| Quiescent current, all converters disabled, LDO1, LDO2 = OFF, Vdd_alive = OFF | Iq | 16 | mA | VCC = 3.6V | 5 | ||
| Quiescent current, all converters disabled, LDO1, LDO2 = OFF, Vdd_alive = ON | Iq | 26 | mA | VCC = 3.6V | 5 | ||
| Input voltage range, VINDCDC1 | VI | 2.5 | 6 | V | 6 | ||
| Maximum output current | IO | 1600 | mA | VO = 3.3V | 6 | ||
| Forward current limit (P- and N-channel) | ILIMF | 1.7 | 1.97 | 2.22 | A | 2.5V < VINMAIN < 6V | 6 |
| Oscillator frequency | fS | 1.95 | 2.25 | 2.55 | MHz | 6 | |
| Fixed output voltage 2.8V | VDCDC1 | -2 | 2 | % | VINDCDC1 = 3.3V to 6V; MODE=0 (PWM/PFM); 3.3V 0 mA ≤ IO ≤ 1.0A | 6 | |
| Fixed output voltage 2.8V | VDCDC1 | -1 | 1 | % | VINDCDC1 = 3.7V to 6V; MODE=1 (PWM); 3.3V 0 mA ≤ IO ≤ 1.0A | 6 | |
| Adjustable output voltage with resistor divider at DEFDCDC1 | VDCDC1 | -2 | 2 | % | VINDCDC1 = VDCDC1 +0.4V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A (PWM/PFM); MODE = 0 | 6 | |
| Adjustable output voltage with resistor divider at DEFDCDC1 | VDCDC1 | -1 | 1 | % | VINDCDC1 = VDCDC1 +0.4V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A (PWM); MODE = 1 | 6 | |
| Input voltage range, VINDCDC2 | VI | 2.5 | 6 | V | 7 | ||
| Maximum output current | IO | 800 | mA | VO = 2.5V | 7 | ||
| Forward current limit (P- and N-channel) | ILIMF | 1 | 1.16 | 1.29 | A | 2.5V < VINDCDC2 < 6V | 7 |
| Oscillator frequency | fS | 1.95 | 2.25 | 2.55 | MHz | 7 | |
| Fixed output voltage 1.8V | VDCDC2 | -2 | 2 | % | VINDCDC2 = 2.5V to 6V; 0 mA ≤ IO ≤ 1.6A; MODE = 0 (PWM/PFM) | 7 | |
| Adjustable output voltage with resistor divider at DEFDCDC2 | VDCDC2 | -2 | 2 | % | VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A (PWM); MODE = 0 | 7 | |
| Adjustable output voltage with resistor divider at DEFDCDC2 | VDCDC2 | -1 | 1 | % | VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A (PWM); MODE = 1 | 7 | |
| Input voltage range, VINDCDC3 | VI | 2.5 | 6 | V | 8 | ||
| Maximum output current | IO | 800 | mA | VO = 1.6V | 8 | ||
| Forward current limit (P- and N-channel) | ILIMF | 1 | 1.2 | 1.4 | A | 2.5V < VINDCDC3 < 6V | 8 |
| Oscillator frequency | fS | 1.95 | 2.25 | 2.55 | MHz | 8 | |
| Adjustable output voltage with resistor divider at DEFDCDC2 | VDCDC3 | -2 | 2 | % | VINDCDC3 = VDCDC3 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 0.8A; MODE = 0 (PWM) | 8 | |
| Adjustable output voltage with resistor divider at DEFDCDC2 | VDCDC3 | -1 | 1 | % | VINDCDC3 = VDCDC3 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 0.8A; MODE = 1 (PWM) | 8 | |
| Operating quiescent current per LDO into VINLDO | I(q) | 16 | 33 | mA | 9 | ||
| Input voltage range for LDO1, LDO2 | VI | 1.5 | 6.5 | V | 9 | ||
| LDO1 output voltage range | VO | 1 | 3.3 | V | 9 | ||
| Maximum output current for LDO1, LDO2 | IO | 200 | mA | VI = 1.8V, VO = 1.3V | 9 | ||
| Minimum voltage drop at LDO1, LDO2 | 65 | 150 | mV | IO = 50mA, VINLDO = 1.5V | 9 | ||
| Output voltage accuracy for LDO1, LDO2 | -2 | 1 | % | IO = 10mA | 9 | ||
| Load regulation for LDO1, LDO2 | -1 | 1 | % | IO = 0mA to 200mA | 9 | ||
| Vdd_alive LDO output voltage | Vdd_alive | 1 | V | IO = 0mA | 9 | ||
| Vdd_alive short circuit current limit | I(SC) | 100 | mA | Vdd_alive = GND | 9 | ||
| Output voltage accuracy for Vdd_alive | -1 | 1 | % | IO = 0mA | 9 | ||
| High level input voltage | VIH | 1.3 | V | DEFDCDC1, DEFDCDC2, DEFDCDC3; max is VCC | 9 | ||
| Low level input voltage | VIL | 0 | 0.1 | V | DEFDCDC1, DEFDCDC2, DEFDCDC3 | 9 | |
| Power fail output low voltage | VOL | 0.3 | V | IOL = 5 mA | 9 | ||
| Thermal resistance junction to ambient, RHB package, high K board | RqJA | 35 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
TPS650250QRHBRQ1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps650250qrhbrq1-etched.step/tps650250qrhbrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps650250qrhbrq1.step/tps650250qrhbrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
54e29206e0125377, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).