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TPS650243QRHBRQ1

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Texas Instruments Battery Management, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps650243qrhbrq1factory-2.0.0extractor-text
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Contents

README

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TPS650243QRHBRQ1

Texas Instruments · Battery Management · VQFN-32-EP(5x5)

TPS650243QRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDCDC3 input VDCDC3 feedback voltage sense input, connect directly to the VDCDC3 output.
2 PGND3 power_in Power ground for the VDCDC3 converter.
3 L3 passive Switch pin of the VDCDC3 converter; the VDCDC3 inductor is connected here.
4 VINDCDC3 power_in Input voltage for the VDCDC3 step-down converter; must be connected to the same supply as VINDCDC1, VINDCDC2 and VCC.
5 VINDCDC1 power_in Input voltage for the VDCDC1 step-down converter; must be connected to the same supply as VINDCDC2, VINDCDC3 and VCC.
6 L1 passive Switch pin of the VDCDC1 converter; the VDCDC1 inductor is connected here.
7 PGND1 power_in Power ground for the VDCDC1 converter.
8 VDCDC1 input VDCDC1 feedback voltage sense input, connect directly to the VDCDC1 output.
9 DEFDCDC1 input Default VDCDC1 voltage select input (0 = 2.80 V, 1 = 3.3 V), or connect a resistor divider between VDCDC1 and GND to set 0.6 V to VINDCDC1.
10 FB_LDO2 input Feedback pin for LDO2.
11 FB_LDO1 input Feedback pin for LDO1.
12 Vdd_alive output Output voltage of the 30-mA Vdd_alive LDO (1.2 V typical).
13 AGND2 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
14 VLDO2 output Output voltage of LDO2.
15 VINLDO power_in Input voltage for LDO1 and LDO2 (1.5 V to 6.5 V).
16 VLDO1 output Output voltage of LDO1.
17 EN_LDO input Enable input for LDO1 and LDO2; logic high enables, logic low disables.
18 EN_DCDC3 input VDCDC3 enable pin; logic high enables the regulator, logic low disables it.
19 EN_DCDC2 input VDCDC2 enable pin; logic high enables the regulator, logic low disables it.
20 EN_DCDC1 input VDCDC1 enable pin; logic high enables the regulator, logic low disables it.
21 PWRFAIL output Open-drain output, active low when the PWRFAIL comparator indicates a low VBAT condition.
22 DEFDCDC2 input Default VDCDC2 voltage select input (0 = 1.8 V, 1 = 2.5 V), or connect a resistor divider between VDCDC2 and GND to set 0.6 V to VINDCDC2.
23 MODE input Selects Power Safe Mode (low, PFM at light loads) or forced PWM mode (high) for DCDC1, DCDC2 and DCDC3.
24 EN_Vdd_alive input Enable input for the Vdd_alive LDO; logic high enables, logic low disables.
25 VDCDC2 input VDCDC2 feedback voltage sense input, connect directly to the VDCDC2 output.
26 PGND2 power_in Power ground for the VDCDC2 converter.
27 L2 passive Switch pin of the VDCDC2 converter; the VDCDC2 inductor is connected here.
28 VINDCDC2 power_in Input voltage for the VDCDC2 step-down converter; must be connected to the same supply as VINDCDC1, VINDCDC3 and VCC.
29 Vcc power_in Power supply for digital and analog circuitry of the DC-DC converters; must be connected to the same supply as VINDCDC1, VINDCDC2 and VINDCDC3.
30 PWRFAIL_SNS input Input for the comparator driving the PWRFAIL output (1.0 V falling threshold).
31 AGND1 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
32 DEFDCDC3 input VDCDC3 default voltage select input; for TPS650243, 0 = 1.0 V and 1 = 1.2 V.
33 PowerPad power_in Exposed thermal pad; connect the power pad to analog ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS650243QRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps650243qrhbrq1-etched.step / tps650243qrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650243qrhbrq1.step / tps650243qrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 a236f4ed8d4e1bb0, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF