component

TPS650241RHBR

Public Made by Adom

by adom

Texas Instruments Battery Management, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps650241rhbrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
tps650241rhbr / README.md
History Download
Ray Publish 0.1.0 3bf4286 19d ago

TPS650241RHBR

Texas Instruments · Battery Management · VQFN-32-EP(5x5)

TPS650241RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDCDC3 input VDCDC3 feedback voltage sense input; connect directly to VDCDC3.
2 PGND3 power_in Power ground for the VDCDC3 converter.
3 L3 passive Switch pin of the VDCDC3 converter; the VDCDC3 inductor (1.5 to 2.2 µH recommended) is connected here.
4 VINDCDC3 power_in Input voltage for the VDCDC3 step-down converter; must be connected to the same supply as VINDCDC1, VINDCDC2 and VCC (recommended range 2.5 V to 6 V).
5 VINDCDC1 power_in Input voltage for the VDCDC1 step-down converter; must be connected to the same supply as VINDCDC2, VINDCDC3 and VCC (recommended range 2.5 V to 6 V).
6 L1 passive Switch pin of the VDCDC1 converter; the VDCDC1 inductor (1.5 to 2.2 µH recommended) is connected here.
7 PGND1 power_in Power ground for the VDCDC1 converter.
8 VDCDC1 input VDCDC1 feedback voltage sense input; connect directly to VDCDC1.
9 DEFDCDC1 input Default VDCDC1 select: GND gives 2.80 V and VCC gives 3.3 V, or a resistor divider from VDCDC1 to GND sets 0.6 V up to VINDCDC1.
10 FB_LDO2 input Feedback pin for LDO2, which sets the LDO2 output (1 V to 3.3 V range).
11 FB_LDO1 input Feedback pin for LDO1, which sets the LDO1 output (1 V to 3.3 V range).
12 Vdd_alive power_out Output of the 30-mA always-on LDO; 1.2 V for the TPS650241 per the voltage options table.
13 AGND2 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
14 VLDO2 power_out Output voltage of LDO2 (200-mA general-purpose LDO).
15 VINLDO power_in Input voltage for LDO1 and LDO2, with an operating range of 1.5 V to 6.5 V.
16 VLDO1 power_out Output voltage of LDO1 (200-mA general-purpose LDO).
17 EN_LDO input Enable input for LDO1 and LDO2; logic high enables the LDOs and logic low disables them.
18 EN_DCDC3 input VDCDC3 enable pin; logic high enables the regulator and logic low disables it.
19 EN_DCDC2 input VDCDC2 enable pin; logic high enables the regulator and logic low disables it.
20 EN_DCDC1 input VDCDC1 enable pin; logic high enables the regulator and logic low disables it.
21 PWRFAIL output Open-drain output that is active low when the PWRFAIL comparator indicates a low VBAT condition.
22 DEFDCDC2 input Default VDCDC2 select: GND gives 1.8 V and VCC gives 2.5 V, or a resistor divider from VDCDC2 to GND sets 0.6 V up to VINDCDC2.
23 MODE input Selects power save mode (PFM at light load, PWM at higher load) when low and forced fixed-frequency PWM mode when high.
24 EN_Vdd_alive input Enable input for the Vdd_alive LDO; logic high enables the LDO and logic low disables it.
25 VDCDC2 input VDCDC2 feedback voltage sense input; connect directly to VDCDC2.
26 PGND2 power_in Power ground for the VDCDC2 converter.
27 L2 passive Switch pin of the VDCDC2 converter; the VDCDC2 inductor (1.5 to 2.2 µH recommended) is connected here.
28 VINDCDC2 power_in Input voltage for the VDCDC2 step-down converter; must be connected to the same supply as VINDCDC1, VINDCDC3 and VCC.
29 VCC power_in Power supply for digital and analog circuitry of the DCDC1, DCDC2 and DCDC3 converters; must be the same supply as VINDCDC1 to VINDCDC3, and the UVLO threshold is 2.35 V.
30 PWRFAIL_SNS input Input for the comparator driving PWRFAIL, compared to a 1 V falling threshold with 50 mV hysteresis.
31 AGND1 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
32 DEFDCDC3 input For the TPS650241, GND sets VDCDC3 to 0.9 V and VCC sets it to 1.375 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS650241RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps650241rhbr-etched.step / tps650241rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650241rhbr.step / tps650241rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 40e3cce5b41a1d8c, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF