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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS65023RSBR

Texas Instruments · Battery Management · WQFN-40-EP(5x5)

TPS65023RSBR from Texas Instruments, in a WQFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DEFDCDC3	input	Input to set VDCDC3 default output to 1.8 V (low) or 3.3 V (high); alternatively connect to resistor divider between VDCDC3 and GND for 0.6 V to VINDCDC3 range.
2	VDCDC3	input	Feedback voltage sense input connected directly to VDCDC3 output for regulation control.
3	PGND3	power_in	Power ground for VDCDC3 converter with internal connection to all GND pins.
4	L3	passive	Switch node connection point for VDCDC3 buck converter inductor with 1 MΩ internal resistance to GND.
5	VINDCDC3	power_in	Input voltage supply (2.5 V to 6 V) for VDCDC3 converter tied to same rail as VINDCDC1, VINDCDC2, and VCC.
6	VINDCDC1	power_in	Input voltage supply (2.5 V to 6 V) for VDCDC1 converter tied to same rail as VINDCDC2, VINDCDC3, and VCC.
7	L1	passive	Switch node connection point for VDCDC1 buck converter inductor with 1 MΩ internal resistance to GND.
8	PGND1	power_in	Power ground for VDCDC1 converter with internal connection to all GND pins.
9	VDCDC1	input	Feedback voltage sense input connected directly to VDCDC1 output for regulation control.
10	DEFDCDC1	input	Input to set VDCDC1 default output to 1.2 V (low) or 1.6 V (high); alternatively connect to resistor divider between VDCDC1 and GND for 0.6 V to VINDCDC1 range.
11	HOT_RESET	input	Push button input with 25-35 ms deglitch time to reset VDCDC1 output to default voltage and generate RESPWRON pulse.
12	DEFLDO1	input	Digital input latched at power-up; combines with DEFLDO2 to set default LDO1 and LDO2 output voltage (four selectable combinations).
13	DEFLDO2	input	Digital input latched at power-up; combines with DEFLDO1 to set default LDO1 and LDO2 output voltage (four selectable combinations).
14	VSYSIN	input	System voltage input with 2.55 V (falling) to 2.65 V (rising) threshold; when above threshold, switches VRTC to VSYSIN through PMOS switch with 375 mV max dropout at 30 mA.
15	VBACKUP	power_in	Backup battery input (2.73 V to 3.75 V) for VRTC supply when VSYSIN is below threshold; connects through PMOS switch with 375 mV max dropout at 30 mA.
16	VRTC	power_out	Real-time clock output providing 3 V at up to 30 mA; priority-selected from VSYSIN, VBACKUP, or internal LDO; triggers RESPWRON when below 2.4 V falling or 2.52 V rising threshold.
17	AGND2	power_in	Analog ground pin; all analog ground pins (AGND1, AGND2) connected internally on the chip.
18	VLDO2	power_out	LDO2 output (200 mA max) with 1 V to 3.3 V selectable range via I2C or DEFLDO pins; maximum dropout 300 mV at 200 mA load.
19	VINLDO	power_in	Input supply voltage (1.5 V to 6.5 V) for LDO1 and LDO2; can power from VCC or DC-DC converter output.
20	VLDO1	power_out	LDO1 output (200 mA max) with 1 V to 3.15 V selectable range via I2C or DEFLDO pins; maximum dropout 300 mV at 200 mA load.
21	LOWBAT	tri_state	Open-drain output from low-battery comparator; active low when LOWBAT_SNS is below 1 V threshold (±1%) with 40-60 mV hysteresis.
22	LDO_EN	input	Enable input for LDO1 and LDO2; logic high enables regulators, logic low (0-0.4 V) disables them.
23	DCDC3_EN	input	Enable input for VDCDC3 converter; logic high (1.3 × VCC minimum) enables regulator, logic low (0-0.4 V) disables it.
24	DCDC2_EN	input	Enable input for VDCDC2 converter; logic high (1.3 × VCC minimum) enables regulator, logic low (0-0.4 V) disables it.
25	DCDC1_EN	input	Enable input for VDCDC1 converter; logic high (1.3 × VCC minimum) enables regulator, logic low (0-0.4 V) disables it.
26	TRESPWRON	input	Timing capacitor input for RESPWRON pulse generation; charges/discharges between 0.25 V and 1 V thresholds at 2 μA for 128 cycles (1 nF = 100 ms).
27	RESPWRON	tri_state	Open-drain system reset output held low until VRTC exceeds 2.52 V threshold, then released for duration set by TRESPWRON capacitor; also triggered by HOT_RESET activation.
28	INT	tri_state	Open-drain power-good output combining all DC-DC and LDO power-good comparators; active low when any enabled supply is out of regulation (10% below target).
29	SDAT	bidirectional	I2C-compatible serial interface data and address line; open-drain with 4.7 kΩ external pullup to VRTC; supports fast mode up to 400 kHz.
30	SCLK	input	I2C-compatible serial interface clock input; open-drain with 4.7 kΩ external pullup to VRTC; supports fast mode up to 400 kHz.
31	PWRFAIL	tri_state	Open-drain power-fail output; active low when PWRFAIL_SNS is below 1 V threshold (±1%) with 40-60 mV hysteresis.
32	DEFDCDC2	input	Input to set VDCDC2 default output to 1.8 V (low) or 3.3 V (high); alternatively connect to resistor divider between VDCDC2 and GND for 0.6 V to VINDCDC2 range.
33	VDCDC2	input	Feedback voltage sense input connected directly to VDCDC2 output for regulation control.
34	PGND2	power_in	Power ground for VDCDC2 converter with internal connection to all GND pins.
35	L2	passive	Switch node connection point for VDCDC2 buck converter inductor with 1 MΩ internal resistance to GND.
36	VINDCDC2	power_in	Input voltage supply (2.5 V to 6 V) for VDCDC2 converter tied to same rail as VINDCDC1, VINDCDC3, and VCC.
37	VCC	power_in	Analog and digital supply voltage (2.5 V to 6 V) for all DC-DC converter control circuits and I2C interface; must connect to same rail as VINDCDC1/2/3.
38	PWRFAIL_SNS	input	Analog input to power-fail comparator with 1 V threshold (±1%) and 40-60 mV hysteresis; drives PWRFAIL open-drain output.
39	LOWBAT_SNS	input	Analog input to low-battery comparator with 1 V threshold (±1%) and 40-60 mV hysteresis; drives LOWBAT open-drain output.
40	AGND1	power_in	Analog ground pin; all analog ground pins (AGND1, AGND2) connected internally on the chip.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-40-EP(5x5)
Category	Power Management (PMIC)
Pins	41

CAD (KiCad official)

Symbol: TPS65023RSBR
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: WQFN-40-EP(5x5) (KiCad packages3D, STEP)
3D model files: tps65023rsbr-etched.step / tps65023rsbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65023rsbr.step / tps65023rsbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (56 pp, sha256 1a96eac1a7a70fa5, retrieved 2026-09-24, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF