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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS650231RSBR

Texas Instruments · Battery Management · WQFN-40(5x5)

TPS650231RSBR from Texas Instruments, in a WQFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DEFDCDC3	input	Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V, or connect to a resistor divider between VDCDC3 and GND to set 0.6 V to VINDCDC3.
2	VDCDC3	input	VDCDC3 feedback voltage sense input, connect directly to VDCDC3.
3	PGND3	power_in	Power ground for the VDCDC3 converter.
4	L3	passive	Switch pin of the VDCDC3 converter where the VDCDC3 inductor is connected.
5	VINDCDC3	power_in	Input voltage for the VDCDC3 step-down converter, must be connected to the same supply as VINDCDC1, VINDCDC2 and VCC.
6	VINDCDC1	power_in	Input voltage for the VDCDC1 step-down converter, must be connected to the same supply as VINDCDC2, VINDCDC3 and VCC.
7	L1	passive	Switch pin of the VDCDC1 converter where the VDCDC1 inductor is connected.
8	PGND1	power_in	Power ground for the VDCDC1 converter.
9	VDCDC1	input	VDCDC1 feedback voltage sense input, connect directly to VDCDC1.
10	DEFDCDC1	input	Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V, or connect to a resistor divider between VDCDC1 and GND to set 0.6 V to VINDCDC1.
11	HOT_RESET	input	Push button input that reboots or wakes up the processor through the RESPWRON output pin.
12	DEFLDO1	input	Digital input that sets the default output voltage of LDO1 and LDO2.
13	DEFLDO2	input	Digital input that sets the default output voltage of LDO1 and LDO2.
14	VSYSIN	power_in	Input of system voltage for the VRTC switch.
15	VBACKUP	power_in	Connect the backup battery to this input pin.
16	VRTC	power_out	Output voltage of the LDO and switch for the real-time clock.
17	AGND2	power_in	Analog ground, all analog ground pins are connected internally on the chip.
18	VLDO2	power_out	Output voltage of LDO2.
19	VINLDO	power_in	Input voltage for LDO1 and LDO2, 1.5 V to 6.5 V.
20	VLDO1	power_out	Output voltage of LDO1.
21	LOW_BAT	output	Open drain output of the LOW_BAT comparator.
22	LDO_EN	input	Enable input for LDO1 and LDO2, logic high enables the LDOs and logic low disables them.
23	DCDC3_EN	input	VDCDC3 enable pin, logic high enables the regulator and logic low disables it.
24	DCDC2_EN	input	VDCDC2 enable pin, logic high enables the regulator and logic low disables it.
25	DCDC1_EN	input	VDCDC1 enable pin, logic high enables the regulator and logic low disables it.
26	TRESPWRON	passive	Connect the timing capacitor here to set the reset delay time, 1 nF gives 100 ms.
27	RESPWRON	output	Open drain system reset output.
28	INT	output	Open drain interrupt output that also serves as a power-OK indication.
29	SDAT	bidirectional	Serial interface data and address line.
30	SCLK	input	Serial interface clock line.
31	PWRFAIL	output	Open drain output, active low when the PWRFAIL comparator indicates a low VBAT condition.
32	DEFDCDC2	input	Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V, or connect to a resistor divider between VDCDC2 and GND to set 0.6 V to VINDCDC2.
33	VDCDC2	input	VDCDC2 feedback voltage sense input, connect directly to VDCDC2.
34	PGND2	power_in	Power ground for the VDCDC2 converter.
35	L2	passive	Switch pin of the VDCDC2 converter where the VDCDC2 inductor is connected.
36	VINDCDC2	power_in	Input voltage for the VDCDC2 step-down converter, must be connected to the same supply as VINDCDC1, VINDCDC3 and VCC.
37	VCC	power_in	Power supply for digital and analog circuitry of the DC-DC converters and the serial interface, must be tied to the same supply as VINDCDC1, VINDCDC2 and VINDCDC3 (2.5 V to 6 V).
38	PWRFAIL_SNS	input	Input for the comparator driving the PWRFAIL output, compared to a 1-V falling threshold with 50 mV hysteresis.
39	LOWBAT_SNS	input	Input for the comparator driving the LOW_BAT output, compared to a 1-V falling threshold with 50 mV hysteresis.
40	AGND1	power_in	Analog ground, all analog ground pins are connected internally on the chip.
41	PowerPAD	power_in	Exposed thermal pad, connect to analog ground and solder to the board.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-40(5x5)
Category	Power Management (PMIC)
Pins	41

CAD (KiCad official)

Symbol: TPS650231RSBR
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: WQFN-40(5x5) (KiCad packages3D, STEP)
3D model files: tps650231rsbr-etched.step / tps650231rsbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650231rsbr.step / tps650231rsbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (57 pp, sha256 22e0b3f3e9072634, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF