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TPS65022RHAR

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Texas Instruments Battery Management, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS65022RHAR

Texas Instruments · Battery Management · VQFN-40-EP(6x6)

TPS65022RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEFDCDC3 input Selects the default VDCDC3 output voltage (0 = 1.3 V, 1 = 1.55 V), and can alternatively be driven from a resistor divider between VDCDC3 and GND for an output in the range 0.6 V to VINDCDC3.
2 VDCDC3 input Feedback voltage sense input for the VDCDC3 step-down converter, to be connected directly to VDCDC3.
3 PGND3 power_in Power ground for the VDCDC3 converter.
4 L3 passive Switch pin of the VDCDC3 converter; the VDCDC3 inductor (2.2 µH to 3.3 µH) connects here.
5 VINDCDC3 power_in Input voltage for the VDCDC3 step-down converter, which must be tied to the same supply as VINDCDC1, VINDCDC2 and VCC (2.5 V to 6 V).
6 VINDCDC1 power_in Input voltage for the VDCDC1 step-down converter, which must be tied to the same supply as VINDCDC2, VINDCDC3 and VCC (2.5 V to 6 V).
7 L1 passive Switch pin of the VDCDC1 converter; the VDCDC1 inductor (2.2 µH to 3.3 µH) connects here.
8 PGND1 power_in Power ground for the VDCDC1 converter.
9 VDCDC1 input Feedback voltage sense input for the VDCDC1 step-down converter, to be connected directly to VDCDC1.
10 DEFDCDC1 input Selects the default VDCDC1 output voltage (0 = 3 V, 1 = 3.3 V), and can alternatively be driven from a resistor divider between VDCDC1 and GND for an output in the range 0.6 V to VINDCDC1.
11 HOT_RESET input Push-button input used to reboot or wake up the processor through the RESPWRON output; it is internally de-bounced (about 30 ms) and resets only VDCDC3 to its DEFDCDC3 default.
12 DEFLDO1 input Digital input that, together with DEFLDO2, sets the default output voltage of LDO1 and LDO2 (latched at power-up; see Table 3).
13 DEFLDO2 input Digital input that, together with DEFLDO1, sets the default output voltage of LDO1 and LDO2 (latched at power-up; see Table 3).
14 VSYSIN power_in Input of the system voltage for the VRTC switch.
15 VBACKUP power_in Input for the backup battery.
16 VRTC power_out Output voltage of the LDO/switch for the real-time clock; it is monitored for the RESPWRON generation (RESPWRON is low when VRTC is below 2.4 V).
17 AGND2 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
18 VLDO2 power_out Output voltage of LDO2 (output current up to 200 mA; output capacitor 2.2 µF).
19 VINLDO power_in Input voltage for LDO1 and LDO2, operating from 1.5 V to 6.5 V.
20 VLDO1 power_out Output voltage of LDO1 (output current up to 200 mA; output capacitor 2.2 µF).
21 LOW_BAT output Open-drain output of the LOW_BAT comparator, which compares LOWBAT_SNS against a 1 V falling threshold with 50 mV hysteresis.
22 LDO_EN input Enable input for LDO1 and LDO2; logic high enables the LDOs and logic low disables them.
23 DCDC3_EN input Enable pin for the VDCDC3 converter; logic high enables the regulator and logic low disables it.
24 DCDC2_EN input Enable pin for the VDCDC2 converter; logic high enables the regulator and logic low disables it.
25 DCDC1_EN input Enable pin for the VDCDC1 converter; logic high enables the regulator and logic low disables it.
26 TRESPWRON passive Connect the timing capacitor here to set the RESPWRON reset delay (1 nF gives typically 100 ms).
27 RESPWRON output Open-drain system reset output, held low at power-up and for the reset delay after VRTC rises above 2.52 V (falling threshold 2.4 V).
28 INT output Open-drain interrupt output that combines the PGOOD comparator outputs of the DC-DC converters and LDOs, acting as a POWER_OK indication.
29 SDAT bidirectional Serial interface data/address line of the I2C-compatible interface (up to 400 kHz).
30 SCLK input Serial interface clock input of the I2C-compatible interface (up to 400 kHz).
31 PWRFAIL output Open-drain output that is driven active low when the PWRFAIL comparator indicates a low VBAT condition (PWRFAIL_SNS compared against a 1 V falling threshold).
32 DEFDCDC2 input Selects the default VDCDC2 output voltage (0 = 1.8 V, 1 = 2.5 V), and can alternatively be driven from a resistor divider between VDCDC2 and GND for an output in the range 0.6 V to VINDCDC2.
33 VDCDC2 input Feedback voltage sense input for the VDCDC2 step-down converter, to be connected directly to VDCDC2.
34 PGND2 power_in Power ground for the VDCDC2 converter.
35 L2 passive Switch pin of the VDCDC2 converter; the VDCDC2 inductor (2.2 µH to 3.3 µH) connects here.
36 VINDCDC2 power_in Input voltage for the VDCDC2 step-down converter, which must be tied to the same supply as VINDCDC1, VINDCDC3 and VCC (2.5 V to 6 V).
37 VCC power_in Power supply for the digital and analog circuitry of the VDCDC1, VDCDC2 and VDCDC3 converters and the serial interface block; it must be tied to the same supply as the VINDCDC pins (2.5 V to 6 V).
38 PWRFAIL_SNS input Input of the comparator driving the PWRFAIL output, with a 1 V falling threshold and 50 mV hysteresis.
39 LOWBAT_SNS input Input of the comparator driving the LOW_BAT output, with a 1 V falling threshold and 50 mV hysteresis.
40 AGND1 power_in Analog ground connection; all analog ground pins are connected internally on the chip.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Power Management (PMIC)
Pins 41

CAD (KiCad official)

  • Symbol: TPS65022RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps65022rhar-etched.step / tps65022rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65022rhar.step / tps65022rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 d9d590408854e8e5, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF