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TPS650006RTER

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Texas Instruments Power Management - Specialized, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps650006rterfactory-2.0.0extractor-text

Verified TPS650006RTER

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS650006RTER · WQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 42-page datasheet
  • ✓distributor: lcsc C2156069, digikey TPS650006RTER-ND, mouser 595-TPS650006RTER
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-wl23rqud/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps650006rter.kicad_sym✓ tps650006rter.kicad_mod✓ tps650006rter.step
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Contents

README

markdown

TPS650006RTER

Texas Instruments · Power Management - Specialized · WQFN-16-EP(3x3)

TPS650006RTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN_LDO1 input Enable LDO1.
2 EN_LDO2 input Enable LDO2.
3 PG output Open-drain active low power good output.
4 PGND power_in Power ground - Connected to the thermal pad.
5 SW output Switch pin - connect inductor here.
6 VINDCDC power_in Input voltage to DC-DC converter and all other control blocks; VIN range from 2.3 V to 6 V.
7 MODE input Selects force PWM or PWM/PFM automatic-transition mode.
8 EN_DCDC input Enable DC-DC converter.
9 FB_DCDC input Voltage to DC-DC error amplifier.
10 AGND power_in Analog ground - Start back to PGND as close to the IC as possible.
11 FB_LDO1 input Voltage to LDO1 error amplifier.
12 VLDO1 power_out LDO1 output voltage; up to 300 mA output current.
13 VINLDO1 power_in Input voltage to LDO1; input voltage range from 1.6 V to 6 V.
14 FB_LDO2 input Voltage to LDO2 error amplifier.
15 VLDO2 power_out LDO2 output voltage; up to 300 mA output current.
16 VINLDO2 power_in Input voltage to LDO2; input voltage range from 1.6 V to 6 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range on all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC -0.3 7 V With respect to AGND 5
Output voltage range -0.3 3.6 V On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC 5
Current 1800 mA VINDCDC, SW, PGND 5
Current 800 mA VINLDO1/2, VLDO1/2, AGND 5
Current at all other pins 1 mA At all other pins 5
Operating free-air temperature TA -40 85 °C Over operating free-air temperature range 5
Maximum junction temperature TJ 125 °C 5
Storage temperature Tstg -65 150 °C 5
SW pin inductor L1 1.5 2.2 3.3 μH 5
Operating ambient temperature TA -40 85 °C 5
Input voltage for VINDCDC of DC-DC converter VIN 2.3 6 V 6
Input voltage for LDO1 VINLDO1 1.6 6 V See (1) 6
Input voltage for LDO2 VINLDO2 1.6 6 V See (1) 6
Internal undervoltage lockout threshold UVLO 1.72 1.77 1.82 V VCC falling 6
Supply current, operating (TPS65000) 23 32 μA MODE low, EN_DCDC high, EN_LDO1/2 low, IOUT = 0 mA and no switching 6
Operating quiescent current IQ 50 57 μA MODE low, EN_DCDC low, EN_LDO1/2 high, IOUT = 0 mA and no switching 6
Shutdown current ISD 0.16 2.2 μA EN_DCDC low, EN_LDO1 and EN_LDO2 low 6
High-level input voltage VIH 1.2 V 7
Low-level input voltage VIL 0.4 V 7
Low-level output voltage VOL 0.4 V PG and RST pins only, IO = -100 μA 7
Input leakage current Ilkg 0.01 0.1 μA MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to GND or VINDCDC 7
Oscillator frequency fSW 1.722 2.25 2.847 MHz 7
High-side MOSFET ON-resistance RDS(on) 240 480 mΩ VINDCDC = VGS = 3.6 V 7
Low-side MOSFET ON-resistance RDS(on) 185 380 mΩ VINDCDC = VGS = 3.6 V 7
DC-output current IO 300 mA 2.3 V ≤ VINDCDC ≤ 2.5 V 7
DC-output current IO 600 mA 2.5 V ≤ VINDCDC ≤ 6 V 7
Forward current limit PMOS and NMOS ILIMF 800 1000 1400 mA 2.3 V ≤ VINDCDC ≤ 6 V 7
Thermal shutdown TSD 150 °C Increasing junction temperature 7
Thermal shutdown hysteresis TSD 30 °C Decreasing junction temperature 7
Output voltage accuracy VDCDC -1.5 0 1.5 % PWM MODE = high, 2.3 V ≤ VINDCDC ≤ 6 V 7
Load regulation (PWM mode) 0.5 % MODE high 7
Input voltage for LDOx VINLDOx 1.6 6 V 7
Continuous pass FET current IO 300 mA 7
Short circuit current limit ISC 340 700 mA 2.3 V ≤ VINLDOx 7
Short circuit current limit ISC 210 700 mA VINLDOx < 2.3 V 7
Dropout voltage VDO 370 mV VINLDOx ≥ 2.3 V, IOUT = 250 mA 7
Output voltage accuracy VLDOx -3.5 3.5 % IO = 1 mA to 300 mA, VINLDOx = 2.3 V to 6 V, VLDOx = 1.2 V 8
Load regulation -1.5 1.5 % IO = 1 mA to 300 mA, VINLDOx = 3.6 V, VLDOx = 1.2 V 8
Line regulation -0.5 0.5 % VINLDOx = 1.6 V to 6 V, VLDOx = 1.2 V at IO = 1 mA 8
Thermal shutdown TSD 150 °C Increasing temperature 8
Thermal shutdown hysteresis TSD 30 °C Decreasing temperature 8
Junction-to-ambient thermal resistance RθJA 44.7 °C/W RTE (WQFN) 16-pin package 6
Junction-to-case (top) thermal resistance RθJC(top) 41.7 °C/W RTE (WQFN) 16-pin package 6
Junction-to-board thermal resistance RθJB 16 °C/W RTE (WQFN) 16-pin package 6
Junction-to-top characterization parameter ψJT 0.4 °C/W RTE (WQFN) 16-pin package 6
Junction-to-board characterization parameter ψJB 16 °C/W RTE (WQFN) 16-pin package 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 4.4 °C/W RTE (WQFN) 16-pin package 6

CAD (KiCad official)

  • Symbol: TPS650006RTER
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps650006rter-etched.step / tps650006rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650006rter.step / tps650006rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 d540e612ccd4d038, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF