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TPS650002TRTERQ1

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Texas Instruments Power Management - Specialized, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS650002TRTERQ1

Texas Instruments · Power Management - Specialized · WQFN-16-EP(3x3)

TPS650002TRTERQ1 from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN_LDO1 input Enable input for LDO1; logic levels are VIH of 1.2 V minimum and VIL of 0.4 V maximum, with enable voltages from 0 V to VINDCDC.
2 EN_LDO2 input Enable input for LDO2; logic levels are VIH of 1.2 V minimum and VIL of 0.4 V maximum, with enable voltages from 0 V to VINDCDC.
3 PG output Open-drain active-low power-good output that is pulled low when all enabled outputs are above 95% of target and goes Hi-Z when an enabled output is below 90%.
4 PGND power_in Power ground, connected to the thermal pad; AGND should star back to PGND as close to the IC as possible.
5 SW output Step-down converter switch pin where the inductor (1.5 µH to 3.3 µH, 2.2 µH typical) connects; absolute maximum is -0.6 V to 7 V, or -2 V to 10 V for 20 ns transients.
6 VINDCDC power_in Input voltage to the DC-DC converter and all other control blocks, specified from 2.3 V to 6 V.
7 MODE input Selects forced-PWM operation when pulled high or automatic PFM/PWM transition when pulled low, with the input range 0 V to VINDCDC.
8 EN_DCDC input Enable input for the DC-DC converter, with enable voltages from 0 V to VINDCDC and the same logic levels as the other enables.
9 FB_DCDC input Voltage feedback input to the DC-DC error amplifier, which must externally connect to the output capacitor.
10 AGND power_in Analog ground, which should star back to PGND as close to the IC as possible.
11 FB_LDO1 input Voltage feedback input to the LDO1 error amplifier, which must externally connect to the output capacitor; absolute maximum is -0.3 V to 3.6 V.
12 VLDO1 power_out LDO1 fixed 2.8 V output, rated for up to 300 mA; absolute maximum is -0.3 V to 3.6 V.
13 VINLDO1 power_in Input voltage to LDO1, specified from 1.6 V to VINDCDC.
14 FB_LDO2 input Voltage feedback input to the LDO2 error amplifier, which must externally connect to the output capacitor; absolute maximum is -0.3 V to 3.6 V.
15 VLDO2 power_out LDO2 fixed 1.2 V output, rated for up to 300 mA; absolute maximum is -0.3 V to 3.6 V.
16 VINLDO2 power_in Input voltage to LDO2, specified from 1.6 V to VINDCDC.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS650002TRTERQ1
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps650002trterq1-etched.step / tps650002trterq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650002trterq1.step / tps650002trterq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 d420eff11d30a216, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF