# TPS62A04ABDRLR

**Texas Instruments** · Global Sourcing Parts · SOT-563

TPS62A04ABDRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin for the device. |
| 2 | SW | output | Switch pin connected to the internal FET switches and the inductor terminal; absolute maximum is -0.3V to VIN+0.3V DC and -3.0V to 10V for transients under 10ns. |
| 3 | VIN | power_in | Power supply voltage pin, operating from 2.5V to 5.5V. |
| 4 | EN | input | Device enable logic input: logic high enables the device, logic low shuts it down, with rising threshold 1.2V and falling threshold 0.4V, and the pin must not be left floating. |
| 5 | FB | input | Feedback pin for the internal control loop, connected to an external feedback divider, with an absolute maximum of 3V. |
| 6 | PG | output | Power-good open-drain output; the pullup resistor cannot be connected to any voltage higher than 5.5V, and if unused it should be left open or connected to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Global Sourcing Parts |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN UVLO rising threshold | VUVLO(R) | 2.3 | 2.4 | 2.5 | V | VIN rising | 5 |
| VIN UVLO falling threshold | VUVLO(F) | 2.2 | 2.3 | 2.4 | V | VIN falling | 5 |
| FB voltage | VFB | 594 | 600 | 606 | mV | TJ = 0°C to 125°C, PWM mode | 5 |
| FB voltage | VFB | 591 | 600 | 609 | mV | PWM mode | 5 |
| VIN quiescent current | IQ(VIN) |  |  | 26 | µA | Non-switching, VEN = High, VFB = 610mV | 5 |
| VIN shutdown supply current | ISD(VIN) |  | 0.01 | 4 | µA | TJ = -40°C to 85°C, VEN = Low | 5 |
| EN voltage rising threshold | VEN(R) | 1.2 |  |  | V | EN rising, enable switching | 5 |
| EN voltage falling threshold | VEN(F) |  |  | 0.4 | V | EN falling, disable switching | 5 |
| EN input leakage current | VEN(LKG) |  |  | 100 | nA | VEN = 5V | 5 |
| FB input leakage current | IFB(LKG) |  |  | 100 | nA | VFB = 0.6V | 5 |
| High-side peak current limit | IHS(OC) | 8.2 |  | 10 | A |  | 5 |
| PG pin leakage current when open drain output is high | IPG(LKG) |  |  | 100 | nA | VPG = 5V | 5 |
| PG pin output low-level voltage |  |  |  | 400 | mV | IPG = 1mA | 5 |
| Switching frequency, FPWM operation | fSW(FCCM) |  | 2200 |  | kHz | VIN = 5V, VOUT = 1.8V | 5 |
| Internal fixed soft-start time |  |  | 0.5 | 1 | ms | From EN = High to VFB = 0.56V | 5 |
| High-side MOSFET on-resistance | RDSON(HS) |  | 15 |  | mΩ | VIN = 5V | 5 |
| Low-side MOSFET on-resistance | RDSON(LS) |  | 10 |  | mΩ | VIN = 5V | 5 |
| Low-side valley current limit | ILS(OC) |  | 9.1 |  | A |  | 5 |
| Power-Good threshold | VPGTH |  | 93.5 |  | % | PG low, FB falling | 5 |
| Power-Good threshold | VPGTH |  | 96 |  | % | PG high, FB rising | 5 |
| PG delay falling |  |  | 30 |  | µs |  | 5 |
| PG delay rising |  |  | 10 |  | µs |  | 5 |
| Output discharge current on SW pin |  |  | 150 |  | mA | VIN = 3.0V, VOUT = 2.0V | 5 |
| Thermal shutdown threshold | TJ(SD) |  | 170 |  | °C | Temperature rising | 5 |
| Thermal shutdown hysteresis | TJ(HYS) |  | 20 |  | °C |  | 5 |
| Input supply voltage range | VIN | 2.5 |  | 5.5 | V |  | 4 |
| Output voltage range | VOUT | 0.6 |  |  | V | Maximum printed as VIN | 4 |
| Effective inductance | L |  | 0.22 |  | µH |  | 4 |
| Effective output capacitance | COUT |  | 120 |  | µF | VOUT < 1.2V | 4 |
| Effective output capacitance | COUT |  | 45 |  | µF | 1.2V <= VOUT < 1.8V | 4 |
| Output current range | IOUT | 0 |  | 4 | A | TPS62A04 | 4 |
| Power-Good input current capability | IPG | 0 |  | 1 | mA |  | 4 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Pin voltage VIN, EN, PG | VIN, EN, PG | -0.3 |  | 6 | V |  | 4 |
| Pin voltage SW DC | SW | -0.3 |  |  | V | DC; maximum printed as VIN + 0.3 V | 4 |
| Pin voltage SW transient | SW | -3 |  | 10 | V | Transient < 10ns | 4 |
| Pin voltage FB | FB | -0.3 |  | 3 | V |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 137.5 |  | °C/W | DRL (SOT563) 6-pin column | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 60.2 |  | °C/W | DRL (SOT563) 6-pin column | 4 |
| Junction-to-board thermal resistance | RθJB |  | 22 |  | °C/W | DRL (SOT563) 6-pin column | 4 |
| Junction-to-top characterization parameter | ψJT |  | 1.4 |  | °C/W | DRL (SOT563) 6-pin column | 4 |
| Junction-to-board characterization parameter | ψJB |  | 21.6 |  | °C/W | DRL (SOT563) 6-pin column | 4 |

## CAD (KiCad official)

- Symbol: `TPS62A04ABDRLR`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `tps62a04abdrlr-etched.step` / `tps62a04abdrlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps62a04abdrlr.step` / `tps62a04abdrlr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps62a04ab.pdf) (22 pp, sha256 `6f3e1a370d0e64e6`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps62a04abdrlr-datasheet.pdf)