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TPS62A01DRLR

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Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tps62a01drlr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps62a01drlr: viewers · Ray 1mo ago
package.json tps62a01drlr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps62a01drlr: specified limits as data (metadata.characteristics, 45 rows from the datasheet) · Ray 26d ago
README.md tps62a01drlr: specified limits as data (metadata.characteristics, 45 rows from the datasheet) · Ray 26d ago
tps62a01drlr-etched.fit.json tps62a01drlr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps62a01drlr-etched.glb tps62a01drlr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps62a01drlr-etched.step tps62a01drlr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps62a01drlr.glb Publish 0.1.0 · Ray 1mo ago
tps62a01drlr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps62a01drlr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps62a01drlr.lbr Publish 0.1.0 · Ray 1mo ago
tps62a01drlr.step Publish 0.1.0 · Ray 1mo ago

TPS62A01DRLR

Texas Instruments · DC-DC Converters · SOT-563

TPS62A01DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 SW output Switch pin connected to internal FET switches and inductor terminal.
3 VIN power_in Input voltage pin for 2.5V to 5.5V supply with input capacitor connection between VIN and GND.
4 EN input Device enable logic input; logic high enables device, logic low disables device and enters shutdown; do not leave floating.
5 FB input Feedback pin for internal control loop with 600mV reference voltage for external feedback divider.
6 PG tri_state Power-good open-drain output pin with pullup resistor limited to 5.5V maximum; leave open or connect to GND if unused.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-563
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pin voltage (VIN, EN, PG) -0.3 6.5 V 4
Pin voltage (SW, DC) -0.3 V 4
Pin voltage (SW, transient) -3 10 V transient < 10 ns 4
Pin voltage (FB) -0.3 3 V 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 150 °C 4
Input supply voltage range VIN 2.5 5.5 V 4
Output voltage range VOUT 0.6 V 4
Output current range (TPS62A01) IOUT 0 1 A TPS62A01 4
Power Good input current capability IPG 0 1 mA 4
Operating junction temperature (recommended) TJ -40 125 °C 4
VIN shutdown supply current ISD(VIN) 0.01 2 µA VEN = Low 5
VIN UVLO rising threshold VUVLO(R) 2.3 2.4 2.5 V VIN rising 5
VIN UVLO falling threshold VUVLO(F) 2.2 2.3 2.4 V VIN falling 5
FB voltage VFB 594 600 606 mV TJ = 0°C to 125°C, PWM mode 5
FB voltage VFB 591 600 609 mV PWM mode 5
High-side peak current limit (TPS62A01) IHS(OC) 1.3 1.8 A TPS62A01 5
VIN quiescent current IQ(VIN) 20 µA Non-switching; VEN = High; VFB = 610 mV; TPS62A01xDRL 5
EN voltage rising threshold VEN(R) 1.2 V EN rising; enable switching 5
EN voltage falling threshold VEN(F) 0.4 V EN falling, disable switching 5
EN input leakage current VEN(LKG) 100 nA VEN = 5 V 5
FB input leakage current IFB(LKG) 100 nA VFB = 0.6 V 5
Switching frequency, FPWM operation fSW(FCCM) 2400 kHz VIN = 5 V; VOUT = 1.8 V 5
Internal fixed soft-start time 1 ms From EN = High to VFB = 0.56 V 5
High-side MOSFET on-resistance (TPS62A01xDRL) RDSON(HS) 180 mΩ TPS62A01xDRL; VIN = 5 V 5
Low-side MOSFET on-resistance (TPS62A01xDRL) RDSON(LS) 120 mΩ TPS62A01xDRL; VIN = 5 V 5
Low-side valley current limit (TPS62A01) ILS(OC) 1.8 A TPS62A01 5
Power Good threshold (PG low, FB falling) VPGTH 93.5 % PG low, FB falling 5
Power Good threshold (PG high, FB rising) VPGTH 96 % PG high, FB rising 5
PG delay falling 35 µs 5
PG delay rising 10 µs 5
PG pin leakage current when open-drain output is high IPG(LKG) 100 nA VPG = 5 V 5
PG pin output low-level voltage 400 mV IPG = 1 mA 5
Output discharge current on SW pin (TPS62A01xDRL) 60 mA VIN = 3 V, VOUT = 2.0 V; TPS62A01xDRL 6
Thermal shutdown threshold TJ(SD) 170 °C Temperature rising 6
Thermal shutdown hysteresis TJ(HYS) 20 °C 6
Output capacitance (VOUT < 1.2 V) COUT 44 µF VOUT < 1.2 V 4
Output capacitance (1.2 V ≤ VOUT < 1.8 V) COUT 22 µF 1.2 V ≤ VOUT < 1.8 V 4
Output capacitance (VOUT ≥ 1.8 V) COUT 10 µF VOUT ≥ 1.8 V 4
Effective inductance L 1 µH 4
Junction-to-ambient thermal resistance (DRL) RθJA 157.3 °C/W DRL 6-pin 4
Junction-to-case (top) thermal resistance (DRL) RθJC(top) 92.2 °C/W DRL 6-pin 4
Junction-to-board thermal resistance (DRL) RθJB 45.6 °C/W DRL 6-pin 4
Junction-to-top characterization parameter (DRL) ψJT 4 °C/W DRL 6-pin 4
Junction-to-board characterization parameter (DRL) ψJB 45 °C/W DRL 6-pin 5

CAD (KiCad official)

  • Symbol: TPS62A01DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: tps62a01drlr-etched.step / tps62a01drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62a01drlr.step / tps62a01drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 cad0b23ab8636891, retrieved 2026-09-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF