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Contents

README

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TPS62A01ADRLR

Texas Instruments · DC-DC Converters · SOT-563

TPS62A01ADRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 SW output Switch pin connected to the internal FET switches and inductor terminal; connect the inductor of the output filter to this pin.
3 VIN power_in Input voltage pin for 2.5V to 5.5V supply range; connect the input capacitor as close as possible between VIN and GND.
4 EN input Device enable logic input; logic high enables the device and logic low disables the device into shutdown; do not leave the pin floating.
5 FB input Feedback pin for the internal control loop; connect this pin to an external feedback divider.
6 PG output Power-good open-drain output pin; the pullup resistor cannot be connected to any voltage higher than 5.5V; if unused, leave the pin open or connect to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-563
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN input supply voltage range VIN 2.5 5.5 V 4
VOUT output voltage range VOUT 0.6 V Maximum printed as VIN (not a number) 4
IOUT output current range, TPS62A01 IOUT 0 1 A TPS62A01 4
IPG Power Good input current capability IPG 0 1 mA 4
Operating junction temperature TJ -40 125 °C 4
VIN, EN, PG pin voltage VIN, EN, PG -0.3 6.5 V Relative to network ground 4
SW, DC pin voltage SW -0.3 V DC; maximum printed as VIN + 0.3 V (not a number) 4
SW pin voltage, transient SW -3 10 V Transient < 10 ns 4
FB pin voltage FB -0.3 3 V 4
TJ Operating junction temperature TJ -40 150 °C 4
Tstg Storage temperature Tstg -55 150 °C 4
VIN UVLO rising threshold VUVLO(R) 2.3 2.4 2.5 V VIN rising 5
VIN UVLO falling threshold VUVLO(F) 2.2 2.3 2.4 V VIN falling 5
FB voltage VFB 594 600 606 mV TJ = 0°C to 125°C, PWM mode 5
FB voltage VFB 591 600 609 mV PWM mode 5
VIN shutdown supply current ISD(VIN) 0.01 2 µA VEN = Low 5
High-side peak current limit, TPS62A01 IHS(OC) 1.3 1.8 A TPS62A01 5
Junction-to-ambient thermal resistance, DRL package RθJA 157.3 °C/W DRL (6 pins) 4
Junction-to-case (top) thermal resistance, DRL package RθJC(top) 92.2 °C/W DRL (6 pins) 4
Junction-to-board thermal resistance, DRL package RθJB 45.6 °C/W DRL (6 pins) 4
Effective inductance L 1 µH Printed as NOM 4
Output capacitance COUT 44 µF VOUT < 1.2 V 4
Output capacitance COUT 22 µF 1.2 V ≤ VOUT < 1.8 V 4
Output capacitance COUT 10 µF VOUT ≥ 1.8 V 4

CAD (KiCad official)

  • Symbol: TPS62A01ADRLR
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: tps62a01adrlr-etched.step / tps62a01adrlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62a01adrlr.step / tps62a01adrlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 cad0b23ab8636891, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF