component
TPS628438DRLR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS628438DRLR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-563
TPS628438DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground power pin, to be connected close to the GND terminals of the input and output capacitors. |
| 2 | VIN | power_in | Power supply input (1.8V to 5.5V) with a ceramic input capacitor required, placed close to this pin for noise and voltage spike suppression. |
| 3 | VSET | input | Connect a resistor (10kΩ to 249kΩ, 1%) to GND to select the predetermined output voltage, with no more than 30pF external capacitance. |
| 4 | EN | input | High level enables the device and low level shuts it down (rising threshold 0.8V, falling 0.4V), with an internal pull-down resistor (about 500kΩ) disabled once the device has started, and must not exceed VIN. |
| 5 | SW | output | Switch pin connected to the internal MOSFET switches, to which the inductor is connected. |
| 6 | VOS | input | Output voltage sense pin for the internal feedback divider and regulation loop, which also discharges VOUT through an internal MOSFET when the converter is disabled and should connect directly to the output capacitor with a short trace. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN pin voltage | VIN | -0.3 | 6 | V | 5 | ||
| SW pin voltage, DC | SW | -0.3 | V | DC, max VIN+0.3V | 5 | ||
| SW pin voltage, transient | SW | -2.5 | 9 | V | transient < 10ns, while switching | 5 | |
| VSET pin voltage | VSET | -0.3 | 6 | V | 5 | ||
| EN pin voltage | EN | -0.3 | 6 | V | 5 | ||
| VOS pin voltage | VOS | -0.3 | 5 | V | 5 | ||
| Operating junction temperature (abs max) | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM, ANSI/ESDA/JEDEC JS-001 | 5 | |
| ESD CDM | V(ESD) | -500 | 500 | V | CDM, ANSI/ESDA/JEDEC JS-002 | 5 | |
| Supply voltage | VIN | 1.8 | 5.5 | V | 5 | ||
| Output current | IOUT | 0.6 | A | 5 | |||
| Effective inductance | L | 0.7 | 1 | 1.2 | µH | 5 | |
| Effective output capacitance | COUT | 4 | 25 | µF | 5 | ||
| Effective input capacitance | CIN | 0.5 | 4.7 | µF | 5 | ||
| External parasitic capacitance on VSET | CVSET | 30 | pF | 5 | |||
| RSET resistance range | RSET | 10 | 249 | kΩ | E96 1% resistors on VSET pin | 5 | |
| RSET E96 resistor tolerance | -1 | 1 | % | external resistor on VSET | 5 | ||
| E96 resistor TCR | TCR | -200 | 200 | ppm/°C | 5 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 138.3 | °C/W | DRL (SOT563) 6-pin | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 57.3 | °C/W | DRL (SOT563) 6-pin | 6 | ||
| Junction-to-board thermal resistance | RθJB | 24.7 | °C/W | DRL (SOT563) 6-pin | 6 | ||
| Junction-to-top characterization parameter | ψJT | 1.4 | °C/W | DRL (SOT563) 6-pin | 6 | ||
| Junction-to-board characterization parameter | ψJB | 24.4 | °C/W | DRL (SOT563) 6-pin | 6 | ||
| Quiescent current (power save mode) | IQ | 275 | 1500 | nA | Non-switching, VEN = VIN, IOUT = 0µA, TJ = -40°C to 85°C | 6 | |
| Quiescent current, switching | IQ | 350 | nA | Switching, VEN = VIN, IOUT = 0µA, VOUT = 0.7V | 6 | ||
| Shutdown current | ISD | 4 | 850 | nA | VEN = 0V, VSET = GND, TJ = -40°C to 85°C | 6 | |
| UVLO rising threshold | VUVLO(R) | 1.75 | 1.8 | V | VIN rising, IOUT = 0µA | 6 | |
| UVLO falling threshold | VUVLO(F) | 1.65 | 1.7 | V | VIN falling, IOUT = 0µA | 6 | |
| UVLO hysteresis | VUVLO(H) | 100 | mV | 6 | |||
| VSET input leakage current | VSET(LKG) | 10 | 800 | nA | TJ = -40°C to 85°C | 6 | |
| VSET high-level detection | VSET(H) | 1 | V | Voltage on VSET during startup | 6 | ||
| RSET accuracy | RSET | -4 | 4 | % | TJ = -20°C to 125°C | 6 | |
| RSET accuracy | RSET | -3.5 | 3.5 | % | TJ = -40°C to 125°C | 6 | |
| EN rising threshold | VEN(R) | 0.8 | V | EN rising, switching enabled | 6 | ||
| EN falling threshold | VEN(F) | 0.4 | V | EN falling, switching disabled | 6 | ||
| EN input leakage current | VEN(LKG) | 1 | 25 | nA | VEN > 0.8V, TJ = -40°C to 85°C | 6 | |
| EN internal pull-down resistance | REN;PD | 425 | 500 | kΩ | EN pin to GND | 6 | |
| DC output voltage accuracy | VOUT | -1 | 1 | % | PWM operation, TJ = -20°C to 125°C | 6 | |
| DC output voltage accuracy | VOUT | -1.5 | 1.5 | % | PWM operation, TJ = -40°C to 125°C | 6 | |
| Output voltage range TPS628438 | VOUT | 1.8 | 3.6 | V | TPS628438 | 6 | |
| VOS input leakage current TPS628438 | IVOS(LKG) | 275 | 450 | nA | TPS628438, VEN = VIN, VVOS = 3.3V, TJ = -40°C to 85°C | 6 | |
| Switching frequency | fSW | 1.5 | MHz | IOUT = 400mA | 6 | ||
| Soft-start time TPS628438 | tSS | 1 | 1.4 | ms | From VOUT = 0% to 95% of nominal | 7 | |
| EN high to start of switching delay | tStartup_delay | 330 | 560 | µs | R2D = GND | 7 | |
| High-side MOSFET on-resistance | RDSON(HS) | 170 | 260 | mΩ | VIN = 3.6V, IOUT = 300mA | 7 | |
| Low-side MOSFET on-resistance | RDSON(LS) | 70 | 115 | mΩ | VIN = 3.6V, IOUT = 300mA | 7 | |
| SW pin leakage current | ILKG_SW | 0 | 35 | nA | VSW = 0.7V, TJ = -40°C to 85°C | 7 | |
| SW pin leakage current | ILKG_SW | 0 | 45 | nA | VSW = 1.2V, TJ = -40°C to 85°C | 7 | |
| High-side peak current limit | IHS(OC) | 0.9 | 1.1 | 1.3 | A | VIN ≥ 2.2V | 7 |
| Low-side valley current limit | ILS(OC) | 0.79 | 1 | 1.11 | A | VIN ≥ 2.2V | 7 |
| Output discharge resistance on VOS | RDSCH_VOS | 7 | 22 | Ω | VEN = GND, I(VOS) = -10mA | 7 | |
| Thermal shutdown threshold | TJ(SD) | 160 | °C | Temperature rising | 7 | ||
| Thermal shutdown hysteresis | TJ(HYS) | 20 | °C | 7 |
CAD (KiCad official)
- Symbol:
TPS628438DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps628438drlr-etched.step/tps628438drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps628438drlr.step/tps628438drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
b91bc83e2e3af5b7, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).