# TPS62840DLCR

**Texas Instruments** · DC-DC Converters · VSON-8(1.5x2)

TPS62840DLCR from Texas Instruments, in a VSON-8(1.5x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | GND supply pin that must be connected close to the GND terminal of the input and output capacitors. |
| 2 | VIN | power_in | Input supply pin with an operating range of 1.8 V to 6.5 V (absolute maximum -0.3 V to 7 V); a 4.7-µF ceramic input capacitor is required close to this pin. |
| 3 | MODE | input | A low level enables Power-Save Mode with automatic PFM/PWM transition and a high level forces PWM mode; the pin can be toggled during operation and must be terminated (absolute maximum -0.3 V to 6.5 V). |
| 4 | EN | input | Enable pin where a high level enables the device and a low level turns it off; it has an internal pulldown of 200 kΩ to 450 kΩ while low (absolute maximum -0.3 V to 6.5 V). |
| 5 | VSET | input | A resistor to GND sets the output voltage when the converter is enabled, with parasitic capacitance to GND kept at or below 100 pF; connect directly to GND for the TPS62849 (absolute maximum -0.3 V to VIN + 0.3 V, below 3.6 V). |
| 6 | STOP | input | A high level stops switching so the output is supplied from the output capacitor, and a low level immediately resumes operation; an internal 450-kΩ pulldown is present and the pin is only available on the DLC package (absolute maximum -0.3 V to 6.5 V). |
| 7 | SW | power_out | Switch pin connected to the internal MOSFET switches where the inductor must be connected (DC -0.3 V to VIN + 0.3 V; AC less than 10 ns -2.0 V to 8.5 V). |
| 8 | VOS | input | Output voltage sense pin for the internal feedback divider and regulation loop that must connect directly to the output capacitor with a short trace, and it discharges VOUT through an internal MOSFET when disabled (absolute maximum -0.3 V to 3.7 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSON-8(1.5x2) |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating quiescent current into pin VIN (DLC package option, device not switching) | IQ_VIN |  | 36 | 100 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V, device not switching, TJ = 25°C | 7 |
| Operating quiescent current into pin VOS (DLC package option, device not switching) | IQ_VOS |  | 56 | 120 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V, device not switching, TJ = 25°C | 7 |
| Operating quiescent current into pin VIN over temperature | IQ_VIN |  | 36 | 360 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V, device not switching, TJ = -40°C to 85°C | 7 |
| Operating quiescent current into pin VOS over temperature | IQ_VOS |  | 56 | 170 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V, device not switching, TJ = -40°C to 85°C | 7 |
| Quiescent current in STOP-related row (label not printed) |  |  | 5 | 100 | nA | EN, STOP = VIN, 3V < VOUT < 3.3V, TJ = -40°C to 85°C | 7 |
| Operating quiescent current into pin VIN in STOP mode | IQ_VIN_STOP |  | 70 | 175 | µA | STOP = High, VOUT = 1.8V, TJ = -40°C to 85°C | 7 |
| Shutdown current into VIN | ISD |  | 25 | 300 | nA | EN = GND, VSET = GND, TJ = -40°C to 85°C | 7 |
| Undervoltage lockout threshold, rising VIN | VTH_UVLO+ | 1.72 | 1.8 |  | V | Rising VIN | 7 |
| Undervoltage lockout threshold, falling VIN | VTH_UVLO- | 1.45 | 1.75 |  | V | Falling VIN | 7 |
| MODE input bias current | IIN |  | 1 | 25 | nA | MODE input, TJ = -40°C to 85°C | 7 |
| Internal pull-down resistance | RPD | 200 | 450 |  | kΩ | EN, STOP inputs | 7 |
| High-side MOSFET on-resistance (DLC, YBG package) | RDS(ON) |  | 430 | 600 | mΩ | VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 8 |
| High-side MOSFET on-resistance (DLC, YBG package) | RDS(ON) |  | 340 | 465 | mΩ | VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Low-side MOSFET on-resistance (DLC, YBG package) | RDS(ON) |  | 170 | 240 | mΩ | VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Low-side MOSFET on-resistance (DLC, YBG package) | RDS(ON) |  | 135 | 180 | mΩ | VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Soft-start switch current limit | ILIMF_SS | 0.15 | 0.225 | 0.3 | A |  | 8 |
| High-side MOSFET switch current limit | ILIMF | 1 | 1.2 | 1.4 | A |  | 8 |
| Output discharge current into VOS pin | IDISCHARGE_VOS | 16 | 35 | 44 | mA | EN = GND, sink current into VOS pin, over VIN range; VOUT = 1.8V, TJ = -40°C to 85°C | 8 |
| Output voltage accuracy (PWM mode) | VOUT | -1.5 | 0 | 1.5 | % | PWM Mode, IOUT = 0 mA, VOUT >= 1.8 V | 8 |
| Output voltage accuracy (PWM mode) | VOUT | -2 | 0 | 2 | % | PWM Mode, IOUT = 0 mA, VOUT <= 1.55 V | 8 |
| Reduced current limit soft-start timeout | tSS_ILIMF |  | 700 | 1200 | µs |  | 8 |
| VIN pin voltage (absolute maximum) | VIN | -0.3 |  | 7 | V | Pin voltage VIN | 6 |
| SW pin voltage DC (absolute maximum) | SW | -0.3 |  |  | V | SW (DC); upper limit printed as VIN + 0.3 V | 6 |
| SW pin voltage AC, less than 10 ns (absolute maximum) | SW | -2 |  | 8.5 | V | SW (AC), less than 10ns | 6 |
| EN, MODE, STOP pin voltage (absolute maximum) | EN, MODE, STOP | -0.3 |  | 6.5 | V |  | 6 |
| VSET pin voltage (absolute maximum) | VSET | -0.3 |  | 3.6 | V | Upper limit printed as VIN + 0.3 and < 3.6 V | 6 |
| VOS pin voltage (absolute maximum) | VOS | -0.3 |  | 3.7 | V |  | 6 |
| Operating junction temperature (absolute maximum) | TJ | -40 |  | 150 | °C |  | 6 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 6 |
| Supply voltage VIN (recommended) | VIN | 1.8 |  | 6.5 | V |  | 6 |
| Effective inductance (recommended) | L | 1.51 | 2.2 | 2.9 | µH |  | 6 |
| Effective output capacitance (recommended) | COUT | 3 | 10 | 40 | µF |  | 6 |
| Effective input capacitance (recommended) | CIN | 1 | 4.7 |  | µF |  | 6 |
| Nominal resistance range for external voltage selection resistor (E96 series) | RSET | 0.909 |  | 267 | kΩ | E96 resistor series | 6 |
| External voltage selection resistor tolerance |  |  |  | 1 | % | External RSET resistor; printed as 1% | 6 |
| External voltage selection resistor temperature coefficient |  | -200 |  | 200 | ppm/°C | External RSET resistor; printed as ±200 ppm/°C | 6 |
| Operating junction temperature range (recommended) | TJ | -40 |  | 125 | °C |  | 6 |
| External parasitic capacitance at VSET pin | CVSET |  |  | 100 | pF | Printed as 100 pF; text states no parasitic capacitance greater than 100 pF | 6 |
| Junction-to-ambient thermal resistance (DLC 8-pin, JEDEC PCB 51-7) | RθJA |  | 105.6 |  | °C/W | 8 Pins DLC package, JEDEC PCB 51-7 | 6 |
| Junction-to-case (top) thermal resistance (DLC 8-pin) | RθJC(top) |  | 75.7 |  | °C/W | 8 Pins DLC package | 6 |
| Junction-to-board thermal resistance (DLC 8-pin) | RθJB |  | 31.9 |  | °C/W | 8 Pins DLC package | 6 |

## CAD (KiCad official)

- Symbol: `TPS62840DLCR`
- Footprint: `Package_SON:VSON-8_1.5x2mm_P0.5mm`
- 3D model: VSON-8(1.5x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps62840dlcr-etched.step` / `tps62840dlcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps62840dlcr.step` / `tps62840dlcr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps62840.pdf) (45 pp, sha256 `b715ae80beb8f08b`, retrieved 2026-11-04, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps62840dlcr-datasheet.pdf)