TPS62821DLCT from Texas Instruments, in a VSON-8(1.5x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Enable input (High=Enabled, Low=Disabled); do not leave floating.
2	FB	input	Output voltage feedback; connect the resistive voltage divider to this pin.
3	AGND	power_in	Signal ground, internally connected to PGND; can be left floating.
4	NC	unconnected	Internally not connected; can be connected to VOUT, GND or left floating.
5	PGND	power_in	Power ground.
6	SW	output	Switch node, connected to the internal MOSFET switches; absolute maximum SW (DC) range is -0.3 V to VIN + 0.3 V.
7	VIN	power_in	Supply voltage; recommended operating range is 2.4 V to 5.5 V.
8	PG	output	Power good output; if unused, leave floating or connect to GND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VSON-8(1.5x2)
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range	VIN	2.4		5.5	V		5
Supply Voltage Range	VIN	2.4		5.5	V		4
Output Voltage Range	VOUT	0.6		4	V		4
Maximum Output Current TPS62821	IOUT			1	A	TPS62821	4
Operating Junction Temperature	TJ	-40		125	°C		4
Pin voltage VIN, FB, EN, PG, NC		-0.3		6	V		4
Pin voltage SW (DC)	SW	-0.3			V	DC; max printed as VIN + 0.3	4
Pin voltage SW (DC, in current limit)	SW	-1			V	DC, in current limit	4
Pin voltage SW (AC)	SW	-2.5		10	V	AC, less than 10ns	4
Power Good Sink Current				1	mA		4
Operating Junction Temperature Range	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Operating Quiescent Current	IQ		4	10	µA	EN=High, IOUT=0A, device not switching	5
Shutdown Current	ISD		0.05	0.5	µA	EN=Low, TJ = -40°C to 85°C	5
Undervoltage Threshold Falling Input Voltage	VUVLO	2.1	2.2	2.3	V	Falling Input Voltage	5
Undervoltage Hysteresis	VUVLO		160		mV		5
Thermal Shutdown Threshold	TSD		150		°C	Rising Junction Temperature	5
Thermal Shutdown Hysteresis	TSD		20		°C		5
High-Level Threshold Voltage (EN)	VH		1		V		5
Low-Level Threshold Voltage (EN)	VL		0.4		V		5
Input Leakage Current (EN, PG)	ILKG		10	100	nA	EN = High, VPG = 5V	5
Soft-Start Time	tSS		1.25		ms	Time from EN=High to 95% of VOUT nominal	5
Power Good Lower Threshold Voltage rising	VPGTL	94	96	98	%	Rising (VFB vs regulation target)	5
Power Good Lower Threshold Voltage falling	VPGTL	90	92	94	%	Falling (VFB vs regulation target)	5
Power Good Upper Threshold Voltage rising	VPGTH	108	110	112	%	Rising (VFB vs regulation target)	5
Power Good Upper Threshold Voltage falling	VPGTH	103	105	107	%	Falling (VFB vs regulation target)	5
Power Good Logic Low Level Output Voltage	VPGL			0.4	V	IPG = -1mA	5
Power Good delay rising	tPGD		100		µs	rising	5
Power Good delay falling	tPGD		20		µs	falling	5
Switching Frequency	FSW		2.2		MHz	PWM Mode Operation	5
High-Side FET ON-Resistance TPS62821	RDS(on)		35		mΩ	TPS62821	5
Low-Side FET ON-Resistance TPS62821,2,3	RDS(on)		25		mΩ	TPS62821,2,3	5
High-Side FET Current Limit TPS62821	ILIM	1.7	2.1	2.4	A	TPS62821	5
Input Leakage Current (FB)	ILKG_FB		10	50	nA	EN=High, VFB=0.6V	5
Feedback Voltage Accuracy	VFB	594	600	606	mV	PWM Mode	5
Output Discharge Current	IDIS		75	400	mA	EN=Low, VSW = 0.4V	5
DC Load Regulation			0.2		%/A	PWM Mode Operation	5
DC Line Regulation			0.05		%/V	PWM Mode Operation	5
Junction-to-ambient thermal resistance	RθJA		114.1		°C/W	JEDEC PCB, DLC (VQFN) 8 pins	4
Junction-to-case (top) thermal resistance	RθJC(top)		90.2		°C/W	DLC (VQFN) 8 pins	4
Junction-to-board thermal resistance	RθJB		43.4		°C/W	DLC (VQFN) 8 pins	4
Junction-to-top characterization parameter	ψJT		6.6		°C/W	JEDEC PCB, DLC (VQFN) 8 pins	4
Junction-to-board characterization parameter	ψJB		43.7		°C/W	JEDEC PCB, DLC (VQFN) 8 pins	4

CAD (KiCad official)

Symbol: TPS62821DLCT
Footprint: Package_SON:VSON-8_1.5x2mm_P0.5mm
3D model: VSON-8(1.5x2) (KiCad packages3D, STEP)
3D model files: tps62821dlct-etched.step / tps62821dlct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62821dlct.step / tps62821dlct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 47217a4e3b559423, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS62821DLCT

Verified TPS62821DLCT

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README