component
TPS62203DBVR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| tps62203dbvr-etched.step | 1d ago |
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TPS62203DBVR
Texas Instruments · DC-DC Converters · SOT-23-5
TPS62203DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VI | power_in | Supply voltage pin of the converter, which must stay within the 2.5 V to 6.0 V recommended input range. |
| 2 | GND | power_in | Ground pin of the device, which the enable and feedback levels are referenced to. |
| 3 | EN | input | Enable pin: pulling it to ground forces shutdown, pulling it to VI enables the device, and it must not be left floating. |
| 4 | FB | input | Feedback pin: connect directly to the output for the fixed-voltage version, or to an external resistor divider for the adjustable version. |
| 5 | SW | bidirectional | Switch pin connected to the internal MOSFET switches, where the inductor is connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VI | 2.5 | 6 | V | 4 | ||
| Output current | IO | 300 | mA | 4 | |||
| Inductor | L | 4.7 | 10 | µH | See Application and Implementation for further information | 4 | |
| Input capacitor | CI | 4.7 | µF | See Application and Implementation for further information | 4 | ||
| Output capacitor | CO | 10 | µF | See Application and Implementation for further information | 4 | ||
| Operating ambient temperature | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Supply voltages | VI | -0.3 | 7 | V | With respect to network ground terminal | 3 | |
| Operating junction temperature | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Junction-to-ambient thermal resistance | RθJA | 220 | °C/W | DBV [SOT-23] 5 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 125 | °C/W | DBV [SOT-23] 5 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 36 | °C/W | DBV [SOT-23] 5 pins | 4 | ||
| Junction-to-top characterization parameter | ψJT | 14 | °C/W | DBV [SOT-23] 5 pins | 4 | ||
| Junction-to-board characterization parameter | ψJB | 35 | °C/W | DBV [SOT-23] 5 pins | 4 | ||
| Input voltage | VI | 2.5 | 6 | V | 5 | ||
| Operating quiescent current | IQ | 15 | 30 | µA | IO = 0 mA, Device is not switching | 5 | |
| Shutdown supply current | 0.1 | 1 | µA | EN = GND | 5 | ||
| Undervoltage lockout threshold | 1.5 | 2 | V | 5 | |||
| EN high level input voltage | 1.3 | V | 5 | ||||
| EN low level input voltage | V(EN) | 0.4 | V | 5 | |||
| EN input bias current | I(EN) | 0.01 | 0.1 | µA | EN = GND or VIN | 5 | |
| P-channel MOSFET on-resistance | rds(ON) | 530 | 690 | mΩ | VIN = VGS = 3.6 V | 5 | |
| P-channel MOSFET on-resistance | rds(ON) | 670 | 850 | mΩ | VIN = VGS = 2.5 V | 5 | |
| N-channel MOSFET on-resistance | rds(ON) | 430 | 540 | mΩ | VIN = VGS = 3.6 V | 5 | |
| N-channel MOSFET on-resistance | rds(ON) | 530 | 660 | mΩ | VIN = VGS = 2.5 V | 5 | |
| P-channel leakage current | Ilkg_(P) | 0.1 | 1 | µA | VDS = 6.0 V | 5 | |
| N-channel leakage current | Ilkg_(N) | 0.1 | 1 | µA | VDS = 6.0 V | 5 | |
| P-channel current limit | I(LIM) | 380 | 480 | 670 | mA | 2.5 V < Vin < 6.0 V | 5 |
| Switching frequency | fS | 650 | 1000 | 1500 | kHz | 5 | |
| Feedback voltage, fixed 3.3 V | VO | 0 | 3 | % | TPS62203, VI = 3.6 V to 6 V, IO = 0 mA | 5 | |
| Feedback voltage, fixed 3.3 V | VO | -3 | 3 | % | TPS62203, VI = 3.6 V to 6 V, 0 mA ≤ IO ≤ 300 mA | 5 | |
| Line regulation | 0.26 | %/V | VI = 2.5 V to 6 V, IO = 10 mA | 5 | |||
| Load regulation | 0.0014 | %/mA | IO = 100 mA to 300 mA | 5 | |||
| Leakage current into SW pin | Ilkg | 0.1 | 1 | µA | Vin > Vout, 0 V ≤ Vsw ≤ Vin | 5 | |
| Reverse leakage current into pin SW | Ilkg(Rev) | 0.1 | 1 | µA | Vin = open, EN = GND, VSW = 6 V | 5 |
CAD (KiCad official)
- Symbol:
TPS62203DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps62203dbvr-etched.step/tps62203dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps62203dbvr.step/tps62203dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
f6ac7e529beda007, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).