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TPS62171DSGR

Texas Instruments · DC-DC Converters · WSON-8-EP(2x2)

TPS62171DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground of the converter.
2 VIN power_in Supply voltage input, specified from 3 V to 17 V in recommended operating conditions.
3 EN input Enable input, High = enabled and Low = disabled.
4 AGND power_in Analog ground, which must be connected to the exposed thermal pad.
5 FB input Voltage feedback of the adjustable version; connect a resistive voltage divider to this pin, and connect it to AGND on fixed-output versions for improved thermal performance.
6 VOS input Output voltage sense pin and connection for the control loop circuitry.
7 SW output Switch node connected to the internal MOSFET switches; the inductor connects between SW and the output capacitor.
8 PG output Open-drain output power good, High = VOUT ready and Low = VOUT below nominal regulation; requires a pull-up resistor and goes high impedance when the device is switched off.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8-EP(2x2)
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pin voltage range VIN VIN -0.3 20 V 4
Pin voltage range EN, SW (DC) EN, SW -0.3 V DC; max printed as VIN+0.3 4
Pin voltage range SW (AC) SW -2 24.5 V less than 10ns 4
Pin voltage range FB, PG, VOS FB, PG, VOS -0.3 7 V 4
Power good sink current PG 10 mA 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD human body model V(ESD) -2000 2000 V HBM, per ANSI/ESDA/JEDEC JS-001 4
ESD charged device model V(ESD) -500 500 V CDM, per JEDEC JESD22-C101 4
Supply voltage VIN 3 17 V 4
Output voltage VOUT 0.9 6 V 4
Operating junction temperature TJ -40 125 °C 4
Input voltage range VIN 3 17 V 5
Operating quiescent current IQ 17 30 µA EN = High, IOUT = 0 mA, device not switching 5
Operating quiescent current IQ 17 25 µA TJ = -40°C to +85°C 5
Shutdown current ISD 1.5 25 µA EN = Low 5
Shutdown current ISD 1.5 4 µA TJ = -40°C to +85°C 5
Undervoltage lockout threshold VUVLO 2.6 2.7 2.82 V Falling input voltage 5
Undervoltage lockout hysteresis VUVLO 180 mV Hysteresis 5
Thermal shutdown temperature TSD 160 °C rising temperature 5
Thermal shutdown hysteresis TSD 20 °C falling temperature 5
Input leakage current (EN) ILKG_EN 0.01 1 µA EN = VIN or GND 5
Power good threshold voltage rising VTH_PG 92 95 98 %VOUT Rising (%VOUT) 5
Power good threshold voltage falling VTH_PG 87 90 93 %VOUT Falling (%VOUT) 5
Power good output low voltage VOL_PG 0.07 0.3 V IPG = -2 mA 5
Input leakage current (PG) ILKG_PG 1 400 nA VPG = 1.8 V 5
High-side MOSFET ON-resistance RDS(ON) 300 600 mΩ VIN ≥ 6 V 5
High-side MOSFET ON-resistance RDS(ON) 430 mΩ VIN = 3 V 5
Low-side MOSFET ON-resistance RDS(ON) 120 200 mΩ VIN ≥ 6 V 5
Low-side MOSFET ON-resistance RDS(ON) 165 mΩ VIN = 3 V 5
High-side MOSFET forward current limit ILIMF 0.85 1.05 1.35 A VIN = 12 V, TJ= 25°C 5
Internal reference voltage VREF 0.8 V 5
Initial output voltage accuracy (PWM) -3 3 % PWM mode operation, VIN ≥ VOUT + 1 V 5
Initial output voltage accuracy (power save) -3.5 4 % Power save mode operation, COUT= 22 µF 5
DC output voltage load regulation 0.05 %/A VIN = 12 V, VOUT = 3.3 V, PWM mode operation 5
DC output voltage line regulation 0.02 %/V 3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 0.5 A, PWM mode operation 5
Junction-to-ambient thermal resistance RθJA 61.8 °C/W 4
Junction-to-case (top) thermal resistance RθJC(top) 61.3 °C/W 4
Junction-to-board thermal resistance RθJB 15.5 °C/W 4
Junction-to-top characterization parameter ψJT 0.4 °C/W 4
Junction-to-board characterization parameter ψJB 15.4 °C/W 4
Junction-to-case (bottom) thermal resistance RθJC(bot) 8.6 °C/W 4

CAD (KiCad official)

  • Symbol: TPS62171DSGR
  • Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
  • 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps62171dsgr-etched.step / tps62171dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62171dsgr.step / tps62171dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 8cb209c1347d758a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF