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page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
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tps62082dsgr-etched.fit.json tps62082dsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tps62082dsgr-etched.glb tps62082dsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tps62082dsgr-etched.step tps62082dsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tps62082dsgr.glb Publish 0.1.0 · Ray 1mo ago
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tps62082dsgr.step Publish 0.1.0 · Ray 1mo ago

TPS62082DSGR

Texas Instruments · DC-DC Converters · WSON-8-EP(2x2)

TPS62082DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Device Enable Logic Input. Logic HIGH enables the device; logic LOW disables the device and puts it into shutdown. Must not be left floating.
2 GND power_in Power and signal ground.
3 MODE input Snooze Mode Enable Logic Input. Logic HIGH enables Snooze Mode; logic LOW disables it. Must not be left floating.
4 FB input Feedback pin for the internal control loop. On adjustable versions connect to an external feedback divider; on fixed-output versions (TPS62082 = 3.3 V fixed) this pin must be left floating or connected to GND.
5 VOS input Output Voltage Sense pin for the internal control loop. Must be connected to the output voltage node.
6 PG output Power Good open-drain output. Pulled low when the output voltage is below regulation limits. May be left floating if unused. Max sink current 0.5 mA.
7 SW power_out Switch pin connected to the internal high-side and low-side MOSFET switches and to the external inductor terminal. Connect the output filter inductor here. Absolute max −1 V to 7 V.
8 VIN power_in Power supply voltage input. Recommended operating range 2.3 V to 6 V; absolute max 7 V. Decouple with a low-ESR ceramic capacitor close to the pin.
9 EP power_in Exposed thermal pad on the bottom of the package. Must be soldered to the PCB GND plane to achieve rated power dissipation and mechanical reliability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8-EP(2x2)
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TPS62082DSGR
  • TPS62082DSGRDSGT

CAD (KiCad official)

  • Symbol: TPS62082DSGR
  • Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
  • 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps62082dsgr-etched.step / tps62082dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62082dsgr.step / tps62082dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 8bcb3930a954521b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF