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tps62061dsgr-etched.glb tps62061dsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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TPS62061DSGR

Texas Instruments · DC-DC Converters · WSON-8-EP(2x2)

TPS62061DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground return for the output stage (internal low-side MOSFET source). Tie to the ground plane using a short, low-impedance connection to the input/output capacitor grounds.
2 SW output Switch node connected to the drain of the internal high-side and low-side MOSFETs. Connect the external power inductor (nominal 1 µH) between this pin and the output capacitor.
3 AGND power_in Analog ground reference for the internal control circuitry. Should be tied to the main device ground (PGND/PowerPAD) with a quiet, low-noise return.
4 FB input Feedback input to the internal regulation loop (reference Vref = 0.6 V). For the fixed 1.8-V TPS62061 variant, connect FB directly to the output capacitor; for adjustable variants connect an external resistor divider from VOUT.
5 EN input Enable input (VIH ≥ 1 V, VIL ≤ 0.4 V, IIN ≤ 1 µA). Drive high to enable the converter, low to place the device in shutdown (ISD < 1 µA, output discharged via internal ~200 Ω resistor). Must not be left floating.
6 MODE input Operating-mode select input. High = forced fixed-frequency PWM operation (low output ripple/noise); Low = power-save mode with automatic PFM/PWM transition for best light-load efficiency. Can be toggled at run time.
7 AVIN power_in Analog VIN supply for the internal control circuitry (2.7 V to 6 V). Must be tied to PVIN and to the input capacitor; a small RC filter to AGND is recommended for noise-sensitive applications.
8 PVIN power_in Power VIN input to the internal high-side MOSFET drain (2.7 V to 6 V, abs-max 7 V). Decouple with a 10-µF ceramic input capacitor placed as close as possible between PVIN and PGND.
9 PowerPAD power_in Exposed thermal pad on the underside of the DSG package. Must be soldered to the PCB land pattern for thermal performance and used as the device ground (tie to PGND/AGND plane).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8-EP(2x2)
Category Power Management (PMIC)
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TPS62061DSGR
  • TPS62061DSGRDSGT

CAD (KiCad official)

  • Symbol: TPS62061DSGR
  • Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
  • 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps62061dsgr-etched.step / tps62061dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62061dsgr.step / tps62061dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 5fe6e6c84fc2c24f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF