# TPS62050DGSR

**Texas Instruments** · DC-DC Converters · VSSOP-10-0.5mm

TPS62050DGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply voltage input for the converter, with a recommended operating range of 2.7 V to 10 V. |
| 2 | LBO | output | Open-drain low battery output that goes logic low to indicate a low battery voltage, with voltage at LBO limited to 6 V. |
| 3 | GND | power_in | Ground reference pin for the device. |
| 4 | PG | output | Open-drain power good output that floats when the output voltage is greater than 95% of nominal and requires a pullup resistor to VOUT. |
| 5 | FB | input | Feedback input for the fixed output voltage option; for the adjustable version an external resistive divider is connected to this pin. |
| 6 | LBI | input | Low battery input to the low battery comparator. |
| 7 | SYNC | input | Synchronization input that accepts an external clock or a connection to GND or VI; SYNC high forces fixed-frequency PWM and SYNC low enables power save mode. |
| 8 | EN | input | Enable input where logic high enables the converter and logic low forces shutdown mode, reducing supply current to less than 2 µA. |
| 9 | SW | output | Switch pin that connects the inductor and the drain of the internal power MOSFETs. |
| 10 | PGND | power_in | Power ground pin to which all power grounds should be connected. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Power Management (PMIC) |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage at VI | VI | 2.7 |  | 10 | V |  | 4 |
| Maximum output current | IO |  |  | 800 | mA | Assuming no thermal limitation | 4 |
| Voltage at PG, LBO |  |  |  | 6 | V |  | 4 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Supply voltage | VI | -0.3 |  | 11 | V |  | 4 |
| Voltage at LBI, FB, LBO, PG |  | -0.3 |  | 7 | V |  | 4 |
| Voltage at SW |  | -0.3 |  | 11 | V |  | 4 |
| Output current | IO |  |  | 850 | mA |  | 4 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input voltage | VI | 2.7 |  | 10 | V |  | 5 |
| Operating quiescent current | I(Q) |  | 12 | 20 | µA | IO = 0 mA, SYNC = GND, VI = 7.2 V | 5 |
| Shutdown current | I(SD) |  | 1.5 | 5 | µA | EN = GND | 5 |
| Shutdown current at TA = 25°C | I(SD) |  | 1.5 | 3 | µA | EN = GND, TA = 25°C | 5 |
| EN high level input voltage | VIH | 1.3 |  |  | V |  | 5 |
| EN low level input voltage | VIL |  |  | 0.3 | V |  | 5 |
| EN input leakage current | Ilkg |  | 0.01 | 0.2 | µA | EN = GND or VIN, VI = 7.2 V | 5 |
| Undervoltage lockout threshold | V(UVLO) |  | 1.6 |  | V |  | 5 |
| P-channel MOSFET ON-resistance | RDS(ON) |  | 400 | 650 | mΩ | VI ≥ 5.4 V; IO = 300 mA | 5 |
| P-channel MOSFET ON-resistance | RDS(ON) |  | 600 | 850 | mΩ | VI = 2.7 V; IO = 300 mA | 5 |
| P-channel MOSFET current limit |  | 1000 | 1200 | 1400 | mA | VI = 7.2 V, VO = 3.3 V | 5 |
| N-channel MOSFET ON-resistance | RDS(ON) |  | 300 | 450 | mΩ | VI ≥ 5.4 V; IO = 300 mA | 5 |
| N-channel MOSFET ON-resistance | RDS(ON) |  | 450 | 550 | mΩ | VI = 2.7 V; IO = 300 mA | 5 |
| PG, LBO output low voltage | VOL |  |  | 0.3 | V | V(FB) = 0.8 × VO nominal, I(sink) = 1 mA | 5 |
| PG, LBO output leakage current |  |  | 0.01 | 0.25 | µA | V(FB) = VO nominal, V(LBI) = VI | 5 |
| Low-battery input trip voltage | V(LBI) |  | 1.21 |  | V | Input voltage falling | 5 |
| Low-battery input hysteresis | V(LBI,HYS) |  | 15 |  | mV |  | 5 |
| LBI leakage current | Ilkg(LBI) |  | 0.01 | 0.1 | µA |  | 5 |
| Oscillator frequency | fS | 600 | 850 | 1000 | kHz |  | 5 |
| Synchronization range | f(SYNC) | 600 |  | 1200 | kHz |  | 5 |
| SYNC high-level input voltage | VIH | 1.5 |  |  | V |  | 5 |
| SYNC low-level input voltage | VIL |  |  | 0.3 | V |  | 5 |
| SYNC input leakage current | Ilkg |  | 0.01 | 0.1 | µA | SYNC = GND or VIN | 5 |
| Duty cycle of external clock signal |  | 20 |  | 90 | % |  | 5 |
| Adjustable output voltage | VO | 0.7 |  | 6 | V | TPS62050, TPS62051 | 5 |
| FB leakage current |  |  | 0.02 | 0.1 | µA | TPS62050, TPS62051 | 5 |
| Feedback voltage tolerance |  | -3 |  | 3 | % | VI = 2.7 V to 10 V, 0 mA < IO < 600 mA | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 154 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `TPS62050DGSR`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `tps62050dgsr-etched.step` / `tps62050dgsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps62050dgsr.step` / `tps62050dgsr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps62050.pdf) (31 pp, sha256 `cdd87ee1343e9356`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps62050dgsr-datasheet.pdf)