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TPS61175PWPR

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by adom

Texas Instruments DC-DC Converters, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tps61175pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps61175pwpr: viewers · Ray 1mo ago
package.json tps61175pwpr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps61175pwpr: specified limits as data (metadata.characteristics, 38 rows from the datasheet) · Ray 25d ago
README.md tps61175pwpr: specified limits as data (metadata.characteristics, 38 rows from the datasheet) · Ray 25d ago
tps61175pwpr-etched.fit.json tps61175pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61175pwpr-etched.glb tps61175pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61175pwpr-etched.step tps61175pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61175pwpr.glb Publish 0.1.0 · Ray 1mo ago
tps61175pwpr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps61175pwpr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps61175pwpr.lbr Publish 0.1.0 · Ray 1mo ago
tps61175pwpr.step Publish 0.1.0 · Ray 1mo ago

TPS61175PWPR

Texas Instruments · DC-DC Converters · HTSSOP-14-EP

TPS61175PWPR from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switching node of the IC, internally driven by power switch; connect to switched side of boost inductor.
2 SW output Switching node of the IC, internally driven by power switch; connect to switched side of boost inductor.
3 VIN power_in Input supply pin for the IC; connect supply voltage between 2.9V and 18V.
4 EN input Enable pin; device disables when voltage falls below enable threshold for more than 10ms.
5 SS output Soft start programming pin; capacitor between SS pin and GND programs soft start timing.
6 SYNC input Switch frequency synchronization pin; external signal 200-2200kHz can synchronize IC switch frequency.
7 AGND power_in Analog signal ground reference for control circuits of the IC.
8 COMP output Output of internal transconductance error amplifier; external RC network connects here for loop compensation.
9 FB input Feedback pin for positive voltage regulation; connect center tap of resistor divider to program output voltage.
10 FREQ output Switch frequency program pin; external resistor connected to set switching frequency 200-2200kHz.
11 NC unconnected No-connect reserved pin; must connect this pin to ground.
12 PGND power_in Power ground of the IC; connected to source of the PWM switch FET.
13 PGND power_in Power ground of the IC; connected to source of the PWM switch FET.
14 PGND power_in Power ground of the IC; connected to source of the PWM switch FET.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14-EP
Category Power Management (PMIC)
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 2.9 18 V 4
Output voltage VO 38 V 4
Inductor L 4.7 47 μH 4
Switching frequency fSW 200 2200 kHz 4
Input capacitor CI 4.7 μF 4
Output capacitor CO 4.7 μF 4
Operating ambient temperature TA -40 85 °C 4
Operating junction temperature TJ -40 125 °C 4
Supply voltage on pin VIN VIN -0.3 20 V 4
Voltage on pin EN -0.3 20 V 4
Voltage on pins FB, FREQ and COMP -0.3 3 V 4
Voltage on pins SYNC, SS -0.3 7 V 4
Voltage on pin SW -0.3 40 V 4
Operating junction temperature range -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, human-body model (HBM) V(ESD) -2000 2000 V Per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged-device model (CDM) V(ESD) -500 500 V Per JEDEC JESD22-C101 4
Input voltage range VIN 2.9 18 V 5
Shutdown current ISD 1.5 μA EN=GND 5
Under-voltage lockout threshold VUVLO 2.5 2.7 V 5
EN logic low voltage Venl 0.4 V VIN = 2.9 V to 18 V 5
EN pull down resistor Ren 400 800 1600 kΩ 5
Voltage feedback regulation voltage VREF 1.204 1.229 1.254 V 5
Error amplifier transconductance Gea 240 340 440 μmho 5
Oscillator frequency fS 0.16 0.21 0.26 MHz Rfreq = 480 kΩ 6
Oscillator frequency fS 1 1.2 1.4 MHz Rfreq = 80 kΩ 6
Oscillator frequency fS 1.76 2.2 2.64 MHz Rfreq = 40 kΩ 6
Maximum duty cycle Dmax 89 % VFB = 1 V, Rfreq = 80 kΩ 6
N-channel MOSFET on-resistance RDS(ON) 0.13 0.25 Ω VIN = VGS = 3.6 V 6
N-channel MOSFET on-resistance RDS(ON) 0.13 0.3 Ω VIN = VGS = 3.0 V 6
N-channel MOSFET current limit ILIM 3 3.8 5 A D = Dmax 6
Thermal shutdown threshold Tshutdown 160 °C 6
Junction-to-ambient thermal resistance RθJA 45.2 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 34.9 °C/W 5
Junction-to-board thermal resistance RθJB 30.1 °C/W 5
Junction-to-top characterization parameter ψJT 1.5 °C/W 5
Junction-to-board characterization parameter ψJB 29.9 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 5.8 °C/W 5

CAD (KiCad official)

  • Symbol: TPS61175PWPR
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
  • 3D model files: tps61175pwpr-etched.step / tps61175pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps61175pwpr.step / tps61175pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 959ace4f06e4ce5d, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF