# TPS61031PWPR

**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP

TPS61031PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | passive | Boost and rectifying switch input, connected to the inductor. |
| 2 | SW | passive | Boost and rectifying switch input, connected to the inductor. |
| 3 | PGND | power_in | Power ground. |
| 4 | PGND | power_in | Power ground. |
| 5 | PGND | power_in | Power ground. |
| 6 | VBAT | power_in | Supply voltage, 1.8 V to 5.5 V recommended operating range. |
| 7 | LBI | input | Low battery comparator input, comparator enabled with EN; absolute maximum 3.6 V. |
| 8 | SYNC | input | Enable/disable power save mode (1/VBAT disabled, 0/GND enabled) or clock signal input for synchronization. |
| 9 | EN | input | Enable input (1/VBAT enabled, 0/GND disabled). |
| 10 | LBO | output | Low battery comparator output (open drain). |
| 11 | GND | power_in | Control/logic ground. |
| 12 | FB | input | Voltage feedback input of adjustable versions. |
| 13 | VOUT | power_out | DC/DC converter output. |
| 14 | VOUT | power_out | DC/DC converter output. |
| 15 | VOUT | power_out | DC/DC converter output. |
| 16 | NC | unconnected | Not connected; no internal connection. |
| 17 | PowerPAD | passive | Exposed thermal pad that must be soldered for appropriate power dissipation and should be connected to PGND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on LBI | VI | -0.3 |  | 3.6 | V |  | 4 |
| Input voltage on SW, VOUT, LBO, VBAT, SYNC, EN, FB | VI | -0.3 |  | 7 | V |  | 4 |
| Maximum junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply voltage at VBAT | VI | 1.8 |  | 5.5 | V |  | 4 |
| Operating ambient temperature range | TA | -40 |  | 85 | °C |  | 4 |
| Operating virtual junction temperature range | TJ | -40 |  | 125 | °C |  | 4 |
| Input voltage range | VI | 1.8 |  | 5.5 | V |  | 5 |
| Oscillator frequency | f | 500 | 600 | 700 | kHz |  | 5 |
| Frequency range for synchronization |  | 500 |  | 700 | kHz |  | 5 |
| Switch current limit |  | 3600 | 4000 | 4500 | mA | VOUT= 5 V | 5 |
| Total accuracy |  | -3 |  | 3 | % |  | 5 |
| Quiescent current into VBAT |  |  | 10 | 25 | µA | IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =5 V | 5 |
| Quiescent current into VOUT |  |  | 10 | 20 | µA | IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =5 V | 5 |
| Shutdown current |  |  | 0.1 | 1 | µA | VEN= 0 V, VBAT = 2.4 V | 5 |
| LBI voltage threshold | VIL | 490 | 500 | 510 | mV | VLBI voltage decreasing | 5 |
| LBI input current |  |  | 0.01 | 0.1 | µA | EN = VBAT or GND | 5 |
| LBO output low voltage |  |  | 0.04 | 0.4 | V | VO = 3.3 V, IOI = 100 µA | 5 |
| LBO output leakage current |  |  | 0.01 | 0.1 | µA | VLBO= 7 V | 5 |
| EN, SYNC input current |  |  | 0.01 | 0.1 | µA | Clamped on GND or VBAT | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 46.9 |  | °C/W | PWP package | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 25.8 |  | °C/W | PWP package | 4 |
| Junction-to-board thermal resistance | RθJB |  | 19.4 |  | °C/W | PWP package | 4 |
| Junction-to-top characterization parameter | ψJT |  | 0.8 |  | °C/W | PWP package | 4 |
| Junction-to-board characterization parameter | ψJB |  | 19.3 |  | °C/W | PWP package | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.2 |  | °C/W | PWP package | 4 |
| SWN switch on resistance |  |  | 55 |  | mΩ | VOUT= 5 V | 5 |
| SWP switch on resistance |  |  | 55 |  | mΩ | VOUT= 5 V | 5 |
| Line regulation |  |  | 0.6 |  | % |  | 5 |
| Load regulation |  |  | 0.6 |  | % |  | 5 |
| Under voltage lockout threshold | VUVLO |  | 1.5 |  | V | VLBI voltage decreasing | 5 |
| LBI input hysteresis |  |  | 10 |  | mV |  | 5 |
| LBO output low current |  |  | 100 |  | µA |  | 5 |
| Overtemperature protection |  |  | 140 |  | °C |  | 5 |
| Overtemperature hysteresis |  |  | 20 |  | °C |  | 5 |

## CAD (KiCad official)

- Symbol: `TPS61031PWPR`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `tps61031pwpr-etched.step` / `tps61031pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps61031pwpr.step` / `tps61031pwpr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps61031) (33 pp, sha256 `09d8799e40eac542`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps61031pwpr-datasheet.pdf)