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TPS61023DRLR
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Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS61023DRLR
Texas Instruments · DC-DC Converters · SOT-563
TPS61023DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Voltage feedback input for the adjustable output voltage, which is set within the 2.2 V to 5.5 V output voltage setting range. |
| 2 | EN | input | Enable logic input: a logic-high voltage enables the device, and a logic-low voltage disables it and puts it into shutdown mode. |
| 3 | VIN | power_in | IC power supply input; the input voltage range is 0.5 V to 5.5 V, with an absolute maximum rating of 7 V on this terminal. |
| 4 | GND | power_in | Ground pin of the IC. |
| 5 | SW | power_out | Switch pin of the converter, connected to the drain of the internal low-side MOSFET and the source of the internal high-side MOSFET; absolute maximum rating is -0.7 V to 7 V (8 V for a 10-ns spike, 9 V for a 1-ns spike). |
| 6 | VOUT | power_out | Boost converter output; the output voltage setting range is 2.2 V to 5.5 V, with an absolute maximum rating of 7 V on this terminal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 0.5 | 5.5 | V | 4 | ||
| Output voltage setting range | VOUT | 2.2 | 5.5 | V | 4 | ||
| Effective inductance range | L | 0.37 | 1 | 2.9 | µH | 4 | |
| Effective input capacitance range | CIN | 1 | 4.7 | µF | 4 | ||
| Effective output capacitance range | COUT | 4 | 10 | 1000 | µF | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Voltage range at terminals VIN, EN, FB, SW, VOUT | -0.3 | 7 | V | 4 | |||
| SW spike | -0.7 | 8 | V | SW spike at 10ns | 4 | ||
| SW spike | -0.7 | 9 | V | SW spike at 1ns | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage range | VIN | 0.5 | 5.5 | V | 5 | ||
| Under-voltage lockout threshold, VIN rising | VIN_UVLO | 1.7 | 1.8 | V | VIN rising | 5 | |
| Under-voltage lockout threshold, VIN falling | VIN_UVLO | 0.4 | 0.5 | V | VIN falling | 5 | |
| Quiescent current into VIN pin | IQ | 0.9 | 3 | µA | IC enabled, No load, No switching, VIN = 1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 85°C | 5 | |
| Quiescent current into VOUT pin | IQ | 20 | 30 | µA | IC enabled, No load, No switching, VOUT = 2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 85°C | 5 | |
| Output voltage setting range | VOUT | 2.2 | 5.5 | V | 5 | ||
| Reference voltage at the FB pin | VREF | 580 | 595 | 610 | mV | PWM mode | 5 |
| Reference voltage at the FB pin | VREF | 585 | 601 | mV | PFM mode | 5 | |
| Output over-voltage protection threshold | VOVP | 5.5 | 5.7 | 6 | V | VOUT rising | 5 |
| Leakage current at FB pin | IFB_LKG | 4 | 20 | nA | TJ = 25°C | 5 | |
| Leakage current into VOUT pin | IVOUT_LKG | 1 | 3 | µA | IC disabled, VIN = 0 V, VSW = 0 V, VOUT = 5.5 V, TJ = 25°C | 5 | |
| Shutdown current into VIN and SW pin | ISD | 0.1 | 0.2 | µA | IC disabled, VIN = VSW = 3.6 V, TJ = 25°C | 5 | |
| Minimum on time | tON_min | 40 | 96 | 130 | ns | 5 | |
| Minimum off time | tOFF_min | 80 | 120 | ns | 5 | ||
| Valley current limit | ILIM_SW | 2.7 | 3.7 | A | VIN = 3.6 V, VOUT = 5.0 V | 5 | |
| Pre-charge current | ILIM_CHG | 200 | 350 | mA | VIN = 1.8 - 5.5 V, VOUT < 0.4 V | 5 | |
| Pre-charge current | ILIM_CHG | 750 | 1200 | mA | VIN = 2.4 V, VOUT = 2.15 V | 5 | |
| EN logic low threshold | VEN_L | 0.35 | 0.42 | 0.45 | V | VIN > 1.8 V or VOUT > 2.2 V | 5 |
| EN logic high threshold | VEN_H | 1.2 | V | VIN > 1.8 V or VOUT > 2.2 V | 5 | ||
| Over-voltage protection hysteresis | VOVP_HYS | 0.1 | V | 5 | |||
| Leakage current at FB pin | IFB_LKG | 6 | nA | TJ = 125°C | 5 | ||
| Soft startup time | tSS | 700 | μs | From active EN to VOUT regulation. VIN = 2.5 V, VOUT = 5.0 V, COUT_EFF = 10μF, IOUT = 0 | 5 | ||
| High-side MOSFET on resistance | RDS(on) | 68 | mΩ | VOUT = 5.0 V | 5 | ||
| Low-side MOSFET on resistance | RDS(on) | 47 | mΩ | VOUT = 5.0 V | 5 | ||
| Switching frequency | fSW | 1 | MHz | VIN = 3.6 V, VOUT = 5.0 V, PWM mode | 5 | ||
| Switching frequency | fSW | 0.5 | MHz | VIN = 1.0 V, VOUT = 5.0 V, PWM mode | 5 | ||
| Thermal shutdown threshold | TSD | 150 | °C | TJ rising | 5 | ||
| Thermal shutdown hysteresis | TSD_HYS | 20 | °C | TJ falling below TSD | 5 | ||
| Junction-to-ambient thermal resistance (first thermal column) | RθJA | 142.7 | °C/W | 4 | |||
| Junction-to-ambient thermal resistance (second thermal column) | RθJA | 91.4 | °C/W | 4 | |||
| Junction-to-case thermal resistance | RθJC | 55.7 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 31 | °C/W | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | For better thermal performance, TI suggest to make copper polygon connected with each pin bigger. | 18 |
CAD (KiCad official)
- Symbol:
TPS61023DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps61023drlr-etched.step/tps61023drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps61023drlr.step/tps61023drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
7e18c6542dc5e1de, retrieved 2026-10-19, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).